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Role : PCIE Characterization Engineer Location : Palo Alto, CA(Full Onsite) 5+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs Hands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5. Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue Working knowledge of signal integrity, SerDes
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