Asic jobs in poway, ca

ASIC/FPGA Verification Engineer III, Secret Clearance

Poway, California

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8d ago

Job Description Join Our Team as a ASIC/FPGA Verification Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in: Denver CO or Highlands Ranch CO Sunnyvale CA You will work a flexible 9x80 schedule in the office full-time. What does this role look like?

Full-time

USD 101,000.00 - 178,135.00 per year

ASIC/FPGA Design Engineer III, Secret Clearance

Poway, California

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8d ago

Job Description Join Our Team as a ASIC/FPGA Design Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in: Sunnyvale CA Denver CO Highlands Ranch CO You will be working a flexible 9x80 schedule in the office full-time. About Lockheed Martin Space Spac

Full-time

USD 101,000.00 - 178,135.00 per year

ASIC DFT Staff Engineer

Remote

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Today

Job Title: ASIC DFT Staff Engineer Location: Remote Job Description: Key Skills: "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical own

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Third Party, Contract

Senior ASIC RTL DESIGN Engineer

Remote or Hybrid in Boston, Massachusetts

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11d ago

12 Months + CONTRACT Starting in September SKILLS: SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation Prefer experience with some of: LPDDR5 UFS/FlashPCIe Gen4/5

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Contract

90 - 130

Lead ASIC DFT Engineer

Remote

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21d ago

Role: Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 10+ yrs to 15 yrs. Job Description: We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts a

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Third Party, Contract

110 - 120

ASIC DTCO, Timing and Technology Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a DTCO and Timing Engineer, you will play a vital role in DTCO analysis targeting the Mobile, Compute, Automotive and IOT markets The candidate will work with best-in-class methodologies, tools and implementation flows/technologies to evaluate process technology entitlement (PPAY) for SOC products at the block/IP-level and at system-level in advanced process technologie

Full-time

USD 140,000.00 - 210,000.00 per year

AI/ML Driven ASIC Design and Implementation Automation Engineer

San Diego, California

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Today

As an AI/ML driven ASIC Design and Implementation Automation Engineer in our Advanced Chip Engineering (ACE) organization, you will work in a dynamic environment to explore methodology, flows and tools to improve efficiency and quality of results (power, performance, area, and quality) for SoC and IP development teams across the organization. You'll be working and connecting with AI/ML and automation experts in the industry as well as academia to explore state-of-the-art AI/ML CAD techniques as

Full-time

USD 147,900.00 - 203,400.00 per year

ASIC Timing and Methodology Engineer

Tijuana, Baja California

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Today

Company: QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT markets The candidate will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm and beyond (process technologies).You will be

Full-time

Lead ASIC DFT Engineer

Remote

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Today

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals

Full-time

Senior Principal ASIC FPGA Engineer

Remote or Boise, Idaho

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Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eli

Full-time

USD 191,146.00 - 212,053.00 per year

ASIC/FPGA Verification Engineer IV

Poway, California

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8d ago

Job Description Join Our Team as a ASIC/FPGA Verification Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in: Sunnyvale CA Denver or Highlands Ranch CO You will be working a flexible 9x80 schedule in the office full-time. About Lockheed Martin Space

Full-time

USD 123,500.00 - 217,695.00 per year

Senior ASIC Emulation Engineer

Remote

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Today

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep

Full-time

USD 170,000.00 - 250,000.00 per year

ASIC/FPGA Verification Engineer III

Poway, California

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8d ago

Full-time

USD 101,000.00 - 178,135.00 per year

PD Engineer

San Diego, California

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19d ago

We''re Hiring: Senior Physical Design (PD) Engineer Location: Bay Area, CA (Onsite) Experience: 8+ Years Sivaltech is looking for an experienced Senior Physical Design (PD) Engineer to join our semiconductor team. If you have expertise in advanced-node ASIC physical design and are passionate about delivering high-quality silicon, we''d love to connect with you! Key ResponsibilitiesPerform end-to-end ASIC physical design implementation from netlist to GDSII. Drive Floorplanning, Placement, Clock

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Full-time, Third Party

180,000 - 200,000

Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

San Diego, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 115,200.00 - 170,390.00 per year

Principal Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

San Diego, California

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Today

Full-time

USD 160,400.00 - 237,320.00 per year

Senior Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

San Diego, California

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Today

Full-time

USD 135,900.00 - 201,130.00 per year

Staff Engineer, ASIC/VLSI Synthesis and Design

San Diego, California

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Today

Full-time

USD 115,200.00 - 170,390.00 per year

Principal Engineer, ASIC/VLSI Synthesis and Design

San Diego, California

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Today

Full-time

USD 160,400.00 - 237,320.00 per year

Design Verification Engineer

San Diego, California

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20d ago

Design Verification EngineerLocation: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job SummaryWe are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC verification to join our semiconductor team. The ideal candidate will have extensive experience in SystemVerilog, UVM, and protocol verification, with a proven track record of developing robust verification environments and achieving coverage closure. Key ResponsibilitiesDevelop and execute comprehensive ve

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Full-time, Third Party

180,000 - 200,000

Asic jobs in Poway, CA, USA