San Jose, California
•
Today
Hi, Hope you are doing well. We do have below position. If interested, kindly repond. Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI) Location: San JoseDuration would be 6 months to start and can be extended to 18 months. OnsiteDepartment: Hardware / SoC DesignLevel: Senior (8+ years) Role Summary We are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub I
Easy Apply
Contract, Third Party
70+










