Ddr sdram jobs in california

Hawthorne, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ELECTRICAL DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshi

Full-time

USD 105,000.00 - 140,000.00 per year

FPGA layout engineer

Pleasanton, California

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Today

Job#: 3043768 Job Description: FPGA Engineer Location: Pleasanton, CA (Onsite) Role Overview We are seeking a Senior FPGA Layout Engineer for an aerospace and defense team. This role requires an individual who can operate independently to develop secure computing products, processor boards, and box-level solutions. The position focuses on laying out complex FPGA- and processor-based boards with minimal ramp-up time. Key Responsibilities Perform complex board layouts for advanced FPGA-based

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Full-time

$80 - $110 per hour

DDR PHY Signal Integrity and Power Integrity Engineer

Santa Clara, California

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2d ago

We are looking for DDR PHY Signal Integrity and Power Integrity Engineer for our client in Santa Clara,CA Job Title: DDR PHY Signal Integrity and Power Integrity Engineer Job Location: Santa Clara,CA Job Type: Contract Job Overview: Pay Range: $71.42hr - $85.71hr Requirement/Must Have: Signal integrity (SI) and power integrity (PI) knowledge, including S-parameter/Z-parameter analysis, channel modeling, and PDN modeling.Knowledge of Ansys or Cadence simulation tools (e.g., HFSS, SIwave, Sigrity,

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Third Party, Contract

Depends on Experience

Senior DFT Engineer

Santa Clara, California

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Today

Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today. We encourage applicants with a history of proven success working in a multic

Full-time

USD 196,000.00 - 310,500.00 per year

PCB Layout Engineer

San Francisco, California

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11d ago

PCB Layout Engineer (High-Speed Server Board Design)Location: Bay Area, CA (Onsite) Duration: 6+ Months (Contract) Job SummaryWe are seeking an experienced PCB Layout Engineer with strong expertise in high-speed PCB layout and server board design. The ideal candidate will have hands-on experience designing complex multilayer server boards and be highly proficient in Cadence Allegro PCB Designer version 22.1 or higher. This role requires close collaboration with hardware, signal integrity, power

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Contract

55 - 58

Design Verification Engineer

San Diego, California

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19d ago

Design Verification EngineerLocation: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job SummaryWe are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC verification to join our semiconductor team. The ideal candidate will have extensive experience in SystemVerilog, UVM, and protocol verification, with a proven track record of developing robust verification environments and achieving coverage closure. Key ResponsibilitiesDevelop and execute comprehensive ve

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Full-time, Third Party

180,000 - 200,000

Lead MTS Applications Engineering

San Jose, California

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Today

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Application Engineer to join our Memory Interface team in San Jose California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Lead MTS Application engineer, the candidate will be reporting to Director of Application and Validation and is a Full-Time position. The engineer will work on developing the v

Full-time

USD 117,300.00 - 167,500.00 per year

Test Engineer-Various Levels

San Jose, California

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Today

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire exceptional Test Engineers to join our Operations team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per wee

Full-time

USD 126,000.00 - 234,000.00 per year

Senior / Principal Layout Engineer - Module Architecture (Pathfinding)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Senior / Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors (DDR6, LPDDR6/LPDDR7, MRDIMM Gen3/Gen4, SOC

Full-time

USD 202,000.00 - 344,000.00 per year

PE Product Engineering

San Jose, California

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Today

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Product Engineering to join our Operations Engineering team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a Product Engineer, you will play a key role in new product introduction. In this full-time position, you will report directly to the Senior Manager of

Full-time

USD 124,000.00 - 230,400.00 per year

DDRSS Validation Engineer (RTL + Silicon Debug)

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Role Overview We are seeking a highly motivated validation engineer with strong debugging and firmware development skills to support next-generation SoC platforms. This role spans pre-silicon verification, emulation, and post-silicon validation, with a focus on deep debug in RTL/Verilog environments and hands-on silicon bring-up. The ideal candidate will bridge the gap be

Full-time

USD 140,000.00 - 210,000.00 per year

Senior SI/PI Engineer - AI and Compute Server Design

Fremont, California

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Today

@HYVE Solutions, missions to help customers, business partners, and employees achieve success through shared goals, strategies, resources and technology solutions. At Hyve Solutions, signal and power integrity are among the most critical disciplines in delivering reliable, high-bandwidth AI and compute servers. As next-generation platforms push PCIe Gen5/Gen6, CXL, NVLink, DDR5/DDR6, and 224G SerDes to their limits, disciplined SI/PI engineering is essential to first-pass success. This role foc

Full-time

USD 127,000.00 - 170,000.00 per year

Field Application Engineer - Radar System

Remote

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Today

Job Title: Field Application Engineer - Radar System Location: Midwest, US Global Sales Introduction: AI is rapidly moving beyond research labs and into the real world-powering advancements in vehicles, factories, hospitals, homes, and everyday devices. NXP's Global Sales organization is the force that transforms our intelligent edge vision into meaningful market impact. We operate on the front lines of innovation, delivering real-world AI, secure edge intelligence, and breakthrough technolog

Full-time

Firmware Engineer Tech Lead

San Jose, California

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Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

USD 160,000.00 - 200,000.00 per year

Principal DDR5 / LPDDR5 PHY Validation Engineer

Santa Clara, California

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Today

Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team - we'd

Full-time

USD 195,000.00 - 292,000.00 per year

Principal Engineer, SOC Integration

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 219,000.00 - 351,000.00 per year

ASIC Implementation Engineer PD

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Pro

Full-time

USD 121,900.00 - 195,000.00 per year

Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect

Mountain View, California

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Today

Lab Summary: The Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high-performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung's strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and reinvent techno

Full-time

USD 179,200.00 - 246,150.00 per year

Senior Engineer, SoC Architecture - Memory Subsystem and Interconnect

Mountain View, California

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Today

Full-time

USD 158,800.00 - 218,100.00 per year

Senior Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect

Mountain View, California

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Today

Full-time

USD 197,800.00 - 296,600.00 per year

Ddr sdram jobs in California, USA