Entry level physical design engineer jobs

Mountain View, California

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5d ago

We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys Fusion Compiler, Innovus, Primetime, Calibre Very Imp S

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Contract

$60 - $70

VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS (10+ Yrs)

Folsom, California

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Today

VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS Folsom, CA 3 + Months Role: Lead block-level physical design from RTL to GDSII. Must Have: 10+ years exp, advanced nodes, and Fusion Compiler. Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the Un

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Contract, Third Party

$90 - $100 per hour

Physical Design Engineer (Synthesis, STA & Floorplanning)

California

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Today

Fulltime Location: Bay Area Visa - Stamped H1B, s. Note: Stamped H1B engineers, who are currently in India and are willing to join us immediately can also be considered. Job Description Physical Design Engineer (Synthesis, STA & Floorplanning) Strong experience in RTL synthesis using Cadence Genus, including SDC constraint development and QoR optimization (timing, area, power) Hands-on expertise in Static Timing Analysis using Cadence Tempus, including setup/hold closure, C scenarios, OCV, an

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Full-time

Physical Design Engineer

Mountain View, California

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5d ago

Employment Eligibility Statement: Due to specific project and client requirements, this position is open to U.S. Citizens and U.S. Lawful Permanent Residents (s). Sponsorship is not available at this time. Danta Technologies evaluates all candidates in compliance with the Immigration and Nationality Act (INA) and EEOC guidelines. All hiring decisions are made without regard to race, color, religion, sex, gender identity, sexual orientation, national origin, age, disability, veteran status, or an

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Contract

$58 - $60

Physical Design Engineer

San Jose, California

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Today

Physical Design Engineer Location: San Jose CA- 5 Days onsite What will you do : * Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure * Setup and Synthesizing RTL * Timing closure through various methods and strategies; preferable in-depth experience in top-level STA * EM/IR Analysis, * Place and Route * Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques * Floor-planning and Layout; preferable in-depth expe

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Full-time

Up to $200,000

physical design engineer

Mountain View, California

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Today

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Contract

Depends on Experience

Physical Design Engineer (Back-Fill Role)

Mountain View, California

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5d ago

Job Title: Physical Design Engineer Location: Mountain View, CA Onsite Openings: 2 Experience: 5 10 Years Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on experience in advanced-node SoC physical design, particularly TSMC 3nm/2nm technologies. The ideal candidate will have experience working on high-performance, low-power SoC/GPU designs and should be capable of owning the physical implementation flow from netlist through GDSII/tapeout. Key Responsib

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Contract

Depends on Experience

Physical Design Engineer

Mountain View, California

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Yesterday

Job Title: Physical Design Engineer Location: Mountain View, CA (Onsite) Experience: 5 -10 years in Physical Design Mandatory Skill: Innovous, 2nm, 3nm, 4nm, 5nm Job Description: Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys Fusion Compiler, In

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Contract

$60 - $70

Physical Design Engineer

Mountain View, California

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2d ago

Job Title: Physical Design Engineer Location: Mountain View, CA (Onsite) We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on

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Third Party, Contract

$60+

Staff Physical Design Engineer

Sunnyvale, California

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28d ago

Required Qualifications: Bachelor s/Master s degree in Electrical Engineering or related field8 12 years of experience in ASIC physical designProven experience in full-chip or large block implementation and tapeoutsStrong expertise in:Floorplanning and power planningPlacement, CTS, routing, and physical verificationStatic Timing Analysis (STA) and timing closureHands-on experience with industry-standard tools such as: Synopsys ICC2 / Cadence InnovusSynopsys PrimeTimeMentor CalibreExperience with

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Third Party, Contract

Depends on Experience

Physical Design Engineer

Austin, Texas

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3d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing clo

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Full-time

Depends on Experience

Physical Design Engineer

San Jose, California

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6d ago

Job Title: Physical Design Engineer Location: San Jose CA Contract We are seeking a Physical Design contractor with strong synthesis and implementationexpertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designsDrive PPA (power, performance, area) optimization through synthesis and earlyimplementation stages. Develop and refine floorplans using Cadence InnovusCollaborate c

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Third Party, Contract

$60 - $80

Physical Design Engineer

San Francisco, California

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7d ago

Physical Design EngineerBay Area, CABelow is the Job Description:Good understanding of Cadence tools (Innovous, Quantus, Voltus).Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route.Experience in developing and implementing Power-grid and high speed clock constraints and specifications.Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.Experience with CDC, stati

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Contract

65 - 75

Physical Design Engineer

Mountain View, California

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Today

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Contract, Third Party

62 - 70

Physical Design Engineer

Mountain View, California

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5d ago

Physical Design Engineer (PnR / PPA / Timing Closure) Mountain View CA Open to Both FTE and Contract Option Salary: Market We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and

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Full-time, Third Party

Depends on Experience

Physical Design Engineer (UPF)

Remote

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11d ago

Title: Physical Design Engineer (UPF) Duration: 3-4 months Location: Remote May need to accommodate some calls with Europe Work Schedule: M-F, 40 hours a week Start Date: 9/21 Project Details: Perform Netlist-to-GDS Physical Design including Place-and-Route, Extraction, STA, Timing/SI/Power/EM/IR analysis & closure and Physical Design Verification (LVS/DRC) Proficiency in using Synopsys tool suites (DC, PT, ICC2) and Calibre for physical verification Adequate programing/scripting skills i

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Third Party, Contract

70 - 85

Physical Design Engineer (Top-Level / Full-Chip) - AS

San Jose, California

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Today

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y

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Full-time

Depends on Experience

Entry Level Mechanical Design Engineer

San Diego, California

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Today

Move Forward with Volt! Volt is immediately hiring for an Entry Level Mechanical Design Engineer in San Diego, CA. As an entry level Mechanical Design Engineer, you will: Create and maintain the Mechanical and Systems composite product design Can cover one or more of composite disciplines; electrical, hydro-mechanical, controls manufacturing, software and display, This position is aimed at the maintenance of Mechanical and Hydro-Mechanical product design This is a Full-Time Temp to Hire opportun

Full-time

USD 30.00 - 32.00 per hour

Physical Design Engineer- senior

Austin, Texas

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what\'s possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (bloc

Full-time

Compensation information provided in the description

CPU Physical Design Engineer, San Diego

San Diego, California

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what\'s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engine

Full-time

Compensation information provided in the description