lec Jobs in california

1 - 9 of 9 Jobs

Senior ASIC Synthesis EngineerJob Title - Senior ASIC Synthesis Engineer

NVIDIA CorporationCompany Name - NVIDIA Corporation

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Remote or Santa Clara, California, USA

Full-time

Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today. We encourage applicants with a history of proven success working

Design Implementation Engineer- GraphicsJob Title - Design Implementation Engineer- Graphics

Qualcomm TechnologiesCompany Name - Qualcomm Technologies

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San Diego, California, USA

Full-time

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: The Design Implementation Engineer will work in Qualcomm's Adreno GPU team and will be responsible for managing all aspect of front end implementation design challenges and methodology. As a member of the Graphics team, the successful applicant will help integrate, implement and deliver state of the art GPU cores and will be working closely with the graphics microarchit

Low Power ASIC Engineer (Next-Gen, High-Speed Memory Subsystem)Job Title - Low Power ASIC Engineer (Next-Gen, High-Speed Memory Subsystem)

Qualcomm TechnologiesCompany Name - Qualcomm Technologies

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San Diego, California, USA

Full-time

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm is the world leader in wireless ICs powering the majority of 4G and 5G devices and the largest fabless semiconductor company in the world. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills, and a focus on low power, high performance ASIC designs, and, ability to execute critical power analysis of critical design IPs for p

Applications Engineering, Sr Staff Engineer - 10787Job Title - Applications Engineering, Sr Staff Engineer - 10787

Synopsys, Inc.Company Name - Synopsys, Inc.

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Sunnyvale, California, USA

Full-time

Descriptions & Requirements Job Description and Requirements We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly

Hardware Design Engineering Intern/ Co-Op (Graduate | Fall 2025 | Hybrid)Job Title - Hardware Design Engineering Intern/ Co-Op (Graduate | Fall 2025 | Hybrid)

AMD (Advanced Micro Devices)Company Name - AMD (Advanced Micro Devices)

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Remote or Austin, Texas, USA

Full-time

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellen

ASIC FPGA Design and Verification Engineer - (Experienced, Lead, or Senior) - MTVJob Title - ASIC FPGA Design and Verification Engineer - (Experienced, Lead, or Senior) - MTV

Boeing CompanyCompany Name - Boeing Company

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Mountain View, California, USA

Full-time

ASIC FPGA Design and Verification Engineer - (Experienced, Lead, or Senior) - MTV Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers (Experienced, Lead, or Senior) to join us as part of our Boeing Electronic Products team at the heart of Boeing's products; ASICs and FPGAs in Mountain View, CA. From complex digitally beamformed phased arrays for constellation satellite programs to c

ASIC and/or FPGA Design & Verification Engineer (Lead, Senior or Principal)Job Title - ASIC and/or FPGA Design & Verification Engineer (Lead, Senior or Principal)

Boeing CompanyCompany Name - Boeing Company

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Huntington Beach, California, USA

Full-time

ASIC and/or FPGA Design & Verification Engineer (Lead, Senior or Principal) Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal) to join us as part of our Boeing Electronic Products team at the heart of Boeing's products; ASICs and FPGAs in Huntington Beach or El Segundo, CA. From complex digitally beamformed phased arrays for constellation satellite prog

STA Engineer/SDC EngineerJob Title - STA Engineer/SDC Engineer

Prismagic Solutions IncCompany Name - Prismagic Solutions Inc

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San Jose, California, USA

Contract

About the Role:Seeking an experienced STA/SDC engineer to own block and full-chip constraints, perform Static Timing Analysis (PrimeTime/Tempus), and collaborate with design and physical design teams for timing closure. Key Skills: Strong expertise in STA and SDC constraints (functional & test modes) Experience with PrimeTime, Tempus, and synthesis tools (Synopsys DC/DCG/FC) Verilog/SystemVerilog design knowledge CDC/glitch analysis (Spyglass CDC), Formal Verification (Formality, LEC) Scripting

STAEngineerJob Title - STAEngineer

CloudiousCompany Name - Cloudious

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San Jose, California, USA

Contract

Position: STA Engineer Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficien