Physical design engineer jobs

Mountain View, California

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21d ago

We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys Fusion Compiler, Innovus, Primetime, Calibre Very Imp S

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Contract

$60 - $70

VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS (10+ Yrs)

Folsom, California

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Today

VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS Folsom, CA 3 + Months Role: Lead block-level physical design from RTL to GDSII. Must Have: 10+ years exp, advanced nodes, and Fusion Compiler. Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the Un

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Contract, Third Party

$90 - $100 per hour

Physical Design Engineer

Remote

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Today

Position: Physical Design Engineer Location: Remote Time Zone: CST Focus: Physical Design | Place & Route (PnR) | PPA Optimization | Timing Closure Key Responsibilities Drive block-level physical design implementation from netlist to GDSII.Perform floorplanning, power planning, placement, CTS, routing, and physical verification.Optimize designs for Power, Performance, and Area (PPA).Achieve timing closure across multiple modes and corners.Analyze and resolve setup, hold, transition, capacitance,

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Third Party, Contract

Depends on Experience

Physical Design Engineer

Remote

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Today

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Contract, Third Party

Depends on Experience

physical design engineer

Mountain View, California

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Today

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Contract

Depends on Experience

Physical Design Engineer || San Jose CA / Austin TX(Onsite)

San Jose, California

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Today

Role: Physical Design Engineer Location: San Jose CA / Austin TX (Onsite) Job description: We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes. Qualifications: Proven experience with large-scale SoC or AI-class designs At least 5 years of PD experience Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below) Strong understanding of timing closure a

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Contract, Third Party

$80

Physical Design Engineer

Austin, Texas

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20d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing clo

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Full-time

Depends on Experience

Physical Design Engineer

San Jose, California

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22d ago

Job Title: Physical Design Engineer Location: San Jose CA Contract We are seeking a Physical Design contractor with strong synthesis and implementationexpertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designsDrive PPA (power, performance, area) optimization through synthesis and earlyimplementation stages. Develop and refine floorplans using Cadence InnovusCollaborate c

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Contract, Third Party

$60 - $80

Physical Design Engineer

San Francisco, California

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Yesterday

Physical Design EngineerBay Area, CABelow is the Job Description:Good understanding of Cadence tools (Innovous, Quantus, Voltus).Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route.Experience in developing and implementing Power-grid and high speed clock constraints and specifications.Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.Experience with CDC, stati

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Contract

65 - 75

ASIC Physical Design Engineer

Lafayette, Indiana

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14d ago

Were hiring for a full-time opportunitywith a leading semiconductor end client in Lafayette, IN. Seeking experienced ASIC Physical Design / Backend Engineers with strong TSMC FinFET tapeout and signoff experience.. Detailed job description is given below. Title:ASIC Physical Design Engineer (TSMC / FinFET) Location: Lafayette, Indiana (Relocation assistance provided) Type: Full time with Client Tapeout , Signoff , DRC/LVS/PEX,Customer interaction Job Responsibilities: Act as the primary inter

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Full-time, Third Party

Depends on Experience

Physical Design Engineer (Top-Level / Full-Chip) - AS

San Jose, California

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Today

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y

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Full-time

Depends on Experience

Sr. Physical Design Engineer, Amazon Leo

Austin, Texas

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Today

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.Be part of Amazon Leo?s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with cus

Full-time

Physical Design Engineer II (IC)

San Jose, California

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Today

Position:Physical Design Engineer II (IC) Job Description:Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.Partner with the design team to proactively identify and

Full-time

Compensation information provided in the description

Physical Design Engineer- senior

Austin, Texas

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what\'s possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (bloc

Full-time

Compensation information provided in the description

CPU Physical Design Engineer, San Diego

San Diego, California

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what\'s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engine

Full-time

Compensation information provided in the description

CPU Physical Design Timing Engineer (Austin, TX)

Austin, Texas

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. About The Role: In this role you will have the oppor

Full-time

Compensation information provided in the description

Manager: Physical Design Engineer

Dallas, Texas

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23d ago

Ready to make a difference? We are seeking a Department Manager, Substation Physical Engineering to lead and grow our substation engineering practice. In this leadership role, you will be responsible for the operational management, technical oversight, staff development, financial performance, and strategic growth of a department delivering substation physical engineering services to utility clients nationwide. You will provide leadership to a multidisciplinary team of substation physical engin

Full-time

USD 174,701.00 - 296,992.00 per year

ASIC Physical Design Engineer

New York, New York

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8d ago

About the Position We are looking to hire an ASIC Physical Design Engineer, who is also experienced reading and writing RTL, to help us design, test and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to l

Full-time

Senior Engineer, Physical Design Engineering (ASIC)

New Jersey

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Today

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's inno

Full-time

USD 116,960.00 - 160,820.00 per year

Staff Engineer, Physical Design

Austin, Texas

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Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 151,000.00 - 226,600.00 per year