Physical design engineer jobs

Physical Design Engineer (Synthesis, STA & Floorplanning)

California

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Today

Fulltime Location: Bay Area Visa - Stamped H1B, s. Note: Stamped H1B engineers, who are currently in India and are willing to join us immediately can also be considered. Job Description Physical Design Engineer (Synthesis, STA & Floorplanning) Strong experience in RTL synthesis using Cadence Genus, including SDC constraint development and QoR optimization (timing, area, power) Hands-on expertise in Static Timing Analysis using Cadence Tempus, including setup/hold closure, C scenarios, OCV, an

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Full-time

Physical Design Engineer

San Jose, California

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20d ago

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering

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Third Party

$$70-$80 C2C

Physical Design Engineer/Static Timing Analysis Engineer

San Diego, California

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29d ago

Urgent position of Physical Design Engineer/Static Timing Analysis Engineer Location San Diego,CA(Onsite) Duration- Long Term We are hiring Static Timing Analysis engineers to strengthen the timing signoff team supporting a leading SoC manufacturer on advanced-node designs. In this role you will own timing constraints, drive block- and full-chip timing closure across all modes and corners, and collaborate closely with the physical design, synthesis, and DFT teams to deliver clean, silicon

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Contract, Third Party

$60 - $65

Staff Physical Design Engineer

Sunnyvale, California

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Today

Required Qualifications: Bachelor s/Master s degree in Electrical Engineering or related field8 12 years of experience in ASIC physical designProven experience in full-chip or large block implementation and tapeoutsStrong expertise in:Floorplanning and power planningPlacement, CTS, routing, and physical verificationStatic Timing Analysis (STA) and timing closureHands-on experience with industry-standard tools such as: Synopsys ICC2 / Cadence InnovusSynopsys PrimeTimeMentor CalibreExperience with

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Third Party, Contract

Depends on Experience

Physical Design Engineer

Mountain View, California

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6d ago

Hi, Job Title: Physical Design Engineer (PnR / PPA / Timing Closure) Location : Mountain View, CA Responsibilities: We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Preferred Qualifications: Bachelor's or Master's degree in Electrical/Electronics Engineering.Experience in advanced nodes (7nm/5nm/3nm preferred).Strong debugging and problem-solving skills.Exp

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Full-time, Third Party

Depends on Experience

ASIC Physical Design Engineer / RTL Synthesis Engineer

Remote

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Yesterday

This is Ganesh from DELLA INFOTECH INC. We have an outstanding opening for you for the opportunity below. Please check the job description and share your updated resume, if you are interested. Hiring: Senior ASIC RTL-to-Physical Design (RTL2PD) / RTL Synthesis Engineer Location: San Jose, CA(onsite) Experience: 8 to 12 years What will Be Doing: RTL Synthesis, Constraint writing, validation, Static timing AnalysisWriting Scripts/Modiying scripts for RTL synthesis, SDC creation, STADebug synthesi

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Third Party, Contract

$60 - $65

AI Silicon Physical Design Engineer

Sunnyvale, California

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Today

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprise

Full-time

USD 150,000.00 - 250,000.00 per year

Physical Design Engineer & DV Engineers

Sunnyvale, California

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15d ago

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Physical Design Engineer – Contract (USC)

Hybrid in San Jose, California

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5d ago

Physical Design Engineer ContractIntroduction: We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering teams. Responsibilities: Execute RTL synthesis for complex ASIC and SoC d

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Contract

75 - 85

Physical Design Engineer (PD/PnR)

Austin, Texas

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25d ago

Job Role -Physical Design Engineer (PD/PnR)Location- Bay Area CA / Austin TX (Hybrid) Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoC designs. Key Responsibilities Perform block-level and top-level Physical Design implementation using Fusion Compiler.Drive flo

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Full-time

130,000 - 140,000

Physical Design Engineer/ Signoff Engineer - CA/ TX - (JK)

Austin, Texas

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25d ago

About the Role We are hiring Static Timing Analysis engineers to strengthen the timing signoff team supporting a leading SoC manufacturer on advanced-node designs. In this role you will own timing constraints, drive block- and full-chip timing closure across all modes and corners, and collaborate closely with the physical design, synthesis, and DFT teams to deliver clean, silicon-ready timing signoff. The ideal candidate has strong fundamentals in static timing analysis, hands-on experience with

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Contract

Depends on Experience

Senior Engineer, Physical Design Engineering (ASIC)

New Jersey

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Today

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's inno

Full-time

USD 116,960.00 - 160,820.00 per year

PD Engineer

Sunnyvale, California

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Today

Senior Physical Design Engineer Sunnyvale, CA, USA Fulltime Visa- G C and U S C Only We are looking for a Senior Physical Design Engineer with 814 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes. This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA. What You will Do: Drive physical design flow: synthesis, floorplanning, placement, CTS, rout

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Full-time

Depends on Experience

Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

Cupertino, California

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Today

AWS Utility Computing (UC) provides product innovations ? from foundational services such as Amazon?s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS?s services and features apart in the industry. As a member of the UC organization, you?ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for

Full-time

ASIC Physical Design Engineer

New York, New York

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5d ago

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking, and research infrastructure. This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think lik

Full-time

Electrical Engineer - Mid Level - Substation Physical Design Focus (Hybrid/Remote)

Remote or Minneapolis, Minnesota

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Today

The role - what you'll do Barr is seeking a substation physical design engineer to join our electrical engineering team. In this hybrid role, you will support the Engineering and Design business unit in interfacing with clients to develop substation physical design deliverables for utility upgrades, including greenfield/brownfield substations, wind facilities, and developer interconnection facilities. You will interface with clients, be responsible for understanding client and internal standard

Full-time

USD 92,000.00 - 125,000.00 per year

Senior Engineer, Digital Design (Physical)

Wilmington, Massachusetts

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Today

Full-time

USD 116,960.00 - 160,820.00 per year

Senior Staff Engineer, Physical Design (Floorplanning)

Austin, Texas

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Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 180,200.00 - 270,400.00 per year

Principal Engineer - Analog and Mixed-Signal Physical Design

Austin, Texas

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Today

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and is responsible for powering Microsoft's Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's online businesses, including Azure, Microsoft 365, Teams, OneDrive, Xbox, and other global services. As Microsoft's cloud and silicon investments continue to grow, the ability to deliver advanced a

Full-time

USD 142,800.00 - 274,800.00 per year

Substation Engineer (Physical Design) - Ohio

Richfield, Ohio

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Today

Job Title : Substation Engineer- Physical Design Location : Richfield, Ohio. Ready to relocate to customer office, WFO Terms: Contract/FTE Duration : Min 1year and possible extension beyond. Education : BE Electrical Domain : Utilities, Infrastructure Short JD : Develop physical engineering and layout design of outdoor Air-Insulated Substations (AIS) and indoor Gas-Insulated Substations (GIS) ranging from 33kV up to 400kV/765kV. Optimize the placement of primary equipment including power

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Full-time, Third Party, Contract