Senior physical design engineer jobs

San Jose, California

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2d ago

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering

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Third Party

$$70-$80 C2C

Physical Design Engineer/Static Timing Analysis Engineer

San Diego, California

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11d ago

Urgent position of Physical Design Engineer/Static Timing Analysis Engineer Location San Diego,CA(Onsite) Duration- Long Term We are hiring Static Timing Analysis engineers to strengthen the timing signoff team supporting a leading SoC manufacturer on advanced-node designs. In this role you will own timing constraints, drive block- and full-chip timing closure across all modes and corners, and collaborate closely with the physical design, synthesis, and DFT teams to deliver clean, silicon

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Contract, Third Party

$60 - $65

Physical Design Engineer

San Jose, California

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Today

Title :: Physical Design Engineer Location :: San Jose, CA Job Type:- Full Time We are seeking a Physical Design Engineer with extensive industry experience to join our world-class silicon engineering team in Sunnyvale, California. This role is designed for highly accomplished engineers who have successfully delivered multiple complex SoCs from architecture through tapeout in advanced technology nodes (7nm, 5nm, 3nm, and below). You will work closely with Architecture, RTL, DFT, Logic Design,

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Full-time

$market rate

Physical Design Engineer

Mountain View, California

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2d ago

Hi, Job Title: Physical Design Engineer (PnR / PPA / Timing Closure) Location : Mountain View, CA Responsibilities: We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Preferred Qualifications: Bachelor's or Master's degree in Electrical/Electronics Engineering.Experience in advanced nodes (7nm/5nm/3nm preferred).Strong debugging and problem-solving skills.Exp

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Full-time, Third Party

Depends on Experience

Physical Design Engineer.

San Diego, California

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Today

Hello, Tittle-Physical Design Engineer Location- San Diego, California, San Jose, CA and Irvine, CA Job Type- Fulltime Physical Design Engineer We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize tha

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Full-time

Hiring - Physical Design Engineer in Santa Clara, CA

Santa Clarita, California

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Today

Hi, Role: Physical Design Engineer Location: Santa Clara, CA Work mode: 5 Days Onsite Fulltime and W2 contracts Any Visa is workable Total 10 positions available, covering all experience levels from Junior to Senior. *Experience:* 4 15 Years Key Responsibilities * Execute end-to-end physical design implementation including: * Floorplanning * Power grid design * Placement & Routing * Clock Tree Synthesis (CTS) * Timing Closure * Signal/Power Integrity Signoff * Physical Verification (D

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Full-time, Contract

Physical Design Engineer & DV Engineers

Sunnyvale, California

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3d ago

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Physical Design Engineer (PD/PnR)

Austin, Texas

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7d ago

Job Role -Physical Design Engineer (PD/PnR)Location- Bay Area CA / Austin TX (Hybrid) Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoC designs. Key Responsibilities Perform block-level and top-level Physical Design implementation using Fusion Compiler.Drive flo

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Full-time

130,000 - 140,000

Physical Design Engineer/ Signoff Engineer - CA/ TX - (JK)

Austin, Texas

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7d ago

About the Role We are hiring Static Timing Analysis engineers to strengthen the timing signoff team supporting a leading SoC manufacturer on advanced-node designs. In this role you will own timing constraints, drive block- and full-chip timing closure across all modes and corners, and collaborate closely with the physical design, synthesis, and DFT teams to deliver clean, silicon-ready timing signoff. The ideal candidate has strong fundamentals in static timing analysis, hands-on experience with

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Contract

Depends on Experience

Front End Physical Design Engineer at Sunnyvale, CA

Sunnyvale, California

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7d ago

This position is for a Physical Design Engineer based in Sunnyvale, CA. The successful candidate will be responsible for driving RTL synthesis and optimization to achieve performance, power, and area goals for complex ASIC/SoC designs. They will work closely with various teams to ensure optimal timing, congestion, and power distribution in the design. ResponsibilitiesDrive RTL synthesis and optimization to achieve performance, power, and area (PPA) goalsPerform floorplanning for complex ASIC/SoC

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Full-time, Third Party

150,000 - 160,000

Physical Design Engineer II (eInfochips Inc)

San Jose, California

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Today

Position:Physical Design Engineer II (eInfochips Inc) Job Description:WhatYou\'llBeDoing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.Partner with the design team to proactively id

Full-time

Physical Design Engineer II (IC)

San Jose, California

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Today

Position:Physical Design Engineer II (IC) Job Description:Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.Partner with the design team to proactively identify and

Full-time

Compensation information provided in the description

AI Silicon Physical Design Engineer

Sunnyvale, California

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Today

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprise

Full-time

USD 150,000.00 - 250,000.00 per year

ASIC Physical Design Engineer

New York, New York

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29d ago

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking, and research infrastructure. This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like

Full-time

Senior Substation Engineer - Physical Design

Austin, Texas

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Today

Stanley Consultants is an award-winning and industry-leading global consulting engineering firm, with an unmatched commitment to culture, values, and ethics. We are dedicated to client experience and solve the most complex challenges to create a sustainable, connected, and enriched world for all. As the world changes, Stanley strategically evolves with it, integrating the latest technology, innovation, and resiliency practices. With over a century of experience serving the energy, federal gover

Full-time

Substation Senior Engineer - Physical Design

Fairfield, Ohio

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Today

Electrical Consultants, Inc. (ECI) is a leading power engineering consultant firm that provides engineering, system planning and studies, technical consultation, project management, surveying, environmental planning, commissioning/testing and construction services to electric utilities, energy developers and industrials throughout the U.S. Our experience includes system voltages from 4.16 kV through 765 kV. ECI has an immediate opening for a Substation Senior Engineer in Fairfield, OH. Responsib

Full-time

SoC Physical Design Engineer, Electrical Analysis

Austin, Texas

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Today

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our pr

Full-time

Senior Staff GPU Physical Design Engineer

Remote

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Today

Job Description Title: Senior Staff GPU Physical Design Engineer Location: Austin, TX or San Jose, CA. onsite strongly preferred Need: GPU or high-performance SoC experience. Advanced node (?5nm). Full block ownership Position Summary We are seeking a Senior Staff GPU Physical Design Engineer for our client to work on the physical implementation of high-performance GPU and system-level IP, driving execution across synthesis, place-and-route, timing closure, and signoff for their advanced tech

Contract

Principal Engineer - Analog and Mixed-Signal Physical Design

Austin, Texas

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Today

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and is responsible for powering Microsoft's Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's online businesses, including Azure, Microsoft 365, Teams, OneDrive, Xbox, and other global services. As Microsoft's cloud and silicon investments continue to grow, the ability to deliver advanced a

Full-time

USD 142,800.00 - 274,800.00 per year

Senior Structural Design Engineer

Houston, Texas

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Today

Senior Structural Design Engineer Needed for Growing International Engineering Firm! This Jobot Job is hosted by: Bryce Koelsch Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $106,000 - $150,000 per year A bit about us: We are an international Engineering firm that employs some of the best and brightest in the field. We are currently on the search for a Senior Structural Design Engineer to join our Design team! Why join us? As a Structur

Full-time

USD 106,000.00 - 150,000.00 per year

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Senior physical design engineer jobs