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Duration: 12+ Months Details: As a member of the CT Server DDR team, we are looking for an experienced signal integrity and power integrity engineer who can be responsible for DDR PHY channel and power delivery network (PDN) architecture, system-level SI/PI, and post-silicon validation. The engineer needs to be hands-on in defining channel and PDN architectures, modelling signal and power delivery at the system level, and validating SI/PI on silicon. The engineer needs to work with design, pack
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Contract
$80 - $85














