Static timing analysis jobs

Austin, Texas

•

30+d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing clo

Easy Apply

Full-time

Depends on Experience

SoC Static Timing Analysis (STA) Engineer, HBM

Folsom, California

•

Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern d

Full-time

USD 198,000.00 - 337,000.00 per year

Physical Design Engineer (Top-Level / Full-Chip) - AS

San Jose, California

•

Yesterday

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y

Easy Apply

Full-time

Depends on Experience

Physical Design Engineer – Lead

San Jose, California

•

14d ago

Position: Physical Design Engineer Lead Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do: Drive ASIC physical design implementation from floorplanning through signoff. Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization. Achieve Power, Performance, and Area (PPA) targets. Develop and validate timing constraints and perform Static Timing Analysis (STA). Execute LEC, VCLP, and EMIR signoff activities. Collaborate with cross-functional

Easy Apply

Full-time

Depends on Experience

Design For Test (DFT) Engineer

San Jose, California

•

Yesterday

Role: Design For Test (DFT) Engineer Location: San Jose, CA (Onsite: M-F) Duration: 6 Months Contract Pay Rate: $100-130/hr W2 Description: Looking for a Design-for-Test contractor to test and validate the next generation chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. Job Responsibilities: Experience with memory BIST Siemens

Easy Apply

Contract

100 - 130

Team Supervisor (Evenings & Overnights)

Florence, Kentucky

•

Today

Soar with us at Wawa. We believe we can make life a little better every day ? one smile, hoagie, or experience at a time. And there?s one secret ingredient that truly sets Wawa apart: Our Associates. At Wawa, you?ll be part of a caring team that?s dedicated to helping all of us fly high ? together. We?re team players, day-brighteners, and go-getters: and we know that Wawa is a place where we can build skills to thrive and open doors to new career opportunities. We?re proud to be a part of a

Full-time

Team Supervisor (Evenings & Overnights)

Lafayette, Indiana

•

Today

Full-time

Team Supervisor (Evenings & Overnights)

Louisville, Kentucky

•

Today

Full-time

Team Supervisor (Evenings & Overnights)