Synopsys jobs in california

Irvine, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. EDA ENGINEER (RFIC ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest sate

Full-time

USD 125,000.00 - 150,000.00 per year

Senior ASIC CAD Engineer

California

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Today

Our Mission At Palo Alto Networks , we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you're ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you're in the right place. Who We Are In order to be the cybersecurity partner of choice, w

Full-time

USD 173,600.00 - 280,700.00 per year

Design Verification (DV) Engineer

Sunnyvale, California

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6d ago

About the role: The DVE is responsible for developing and verifying silicon IP. The DVE should have hands-on experience taking leading-edge digital silicon IP from idea to bring-up, working with Architecture/Micro-architecture, PD, and Software teams. This is an on-site role and will require presence in the office 5 days a week. No hybrid option is available. What you'll do: Develop, optimize, and verify digital silicon IP using an existing C or Python modelCreate and maintain specifications, b

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Third Party, Contract

Depends on Experience

ASIC Design Hardware Engineer - SDC/STA - San Jose, CA (Hybrid)

Hybrid in San Jose, California

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4d ago

ASIC Design Hardware Engineer - SDC/STA (Hybrid) Location: San Jose, California, United States of America You are a diligent Design / SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will develop timing constrains at both block level and fu

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Third Party, Contract

$70+

IT Project Manager

San Jose, California

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Today

10 - IT Project Manager 2 1 Req ID: 137549 Hiring Manager: Grace Rodriguez Santos Band: 10 Region: Americas Country: USA State/Province: California City: San Jose General Overview Functional Area: Information Technology (ITM) Career Stream: IT Project Management (PRM) Role: Manager 2 (MG2) Job Title: IT Project Manage Job Code: MG2-ITM-PROJ Job Level: Level 10 Direct/Indirect Indicator: Indirect Summary We are seeking an experienced and execution-driven IT Project Manager for HP

Full-time

USD 122,761.00 - 191,406.00 per year

Senior Emulation/Verification Engineer In Bay Area, CA || Hybrid Role

Hybrid in Menlo Park, California

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Today

Role: Senior Emulation/Verification EngineerDuration: Long TermLocation: Bay Area, CA || Hybrid Role Job Description-: We are seeking an experienced Senior Emulation/Verification Engineer with expertise in simulation acceleration, hardware emulation, and SystemVerilog/UVM-based verification environments. The ideal candidate will have strong experience with Cadence Palladium and/or Synopsys ZeBu, enabling efficient pre-silicon verification and accelerating complex SoC validation.

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Contract

Depends on Experience

Staff Physical Design Engineer

Sunnyvale, California

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6d ago

Required Qualifications: Bachelor s/Master s degree in Electrical Engineering or related field8 12 years of experience in ASIC physical designProven experience in full-chip or large block implementation and tapeoutsStrong expertise in:Floorplanning and power planningPlacement, CTS, routing, and physical verificationStatic Timing Analysis (STA) and timing closureHands-on experience with industry-standard tools such as: Synopsys ICC2 / Cadence InnovusSynopsys PrimeTimeMentor CalibreExperience with

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Contract, Third Party

Depends on Experience

RTL Design / Microarchitecture Engineer

Sunnyvale, California

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6d ago

Required Qualifications: Bachelor s/Master s degree in Electrical Engineering or related field5 10 years of experience in RTL design and microarchitectureStrong expertise in RTL design using SystemVerilog/VerilogMicroarchitecture development for complex digital systemsPerformance optimization and pipelining techniquesExperience with simulation and debugging tools such as:Synopsys VCS / Cadence XceliumFamiliarity with synthesis and timing concepts (e.g., using Synopsys Design Compiler)Strong unde

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Contract, Third Party

Depends on Experience

CAD and PPA Methodology Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a member of the Graphics team, the successful applicant will help develop new flows/methodologies and algorithms to improve power, performance and area (PPA) on state-of-the-art GPU cores while working closely with the graphics microarchitecture design and implementation teams. The successful candidate will possess basic understanding of RTL design and ASIC design

Full-time

USD 161,800.00 - 242,600.00 per year

MBIST Staff Engineer

Remote

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Today

Job Title: MBIST Staff Engineer Location: Remote Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST in

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Third Party, Contract

Graphics ASICS Hardware Design Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: At Qualcomm, we believe in the power of technology. For decades, our innovations have transformed entire industries, improved billions of lives, and addressed many of society's biggest challenges. With the world becoming increasingly connected, we have a tremendous opportunity to shape a better future. As an R&D engine that has revolutionized the way people connect, ou

Full-time

USD 195,200.00 - 292,800.00 per year

Senior Emulation Engineer

San Francisco, California

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2d ago

Senior Emulation EngineerExperience: 8+ Years Location: Bay Area, CA Duration: Long Term Contract Key skills: palladium or veloce or zebu, timing closure, PCIe, usb Job DescriptionWe are looking for a Senior Emulation Engineer with strong experience in hardware emulation and SoC/ASIC verification. Required Skills8+ years of experience in Hardware Emulation / SoC VerificationHands-on experience with Cadence Palladium, Siemens Veloce, or Synopsys ZeBuStrong experience in emulation bring-up, debugg

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Contract, Third Party

Depends on Experience

Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

San Jose, California

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19d ago

Hello Professional, Good Afternoon Please find the job description give below, if interested please share me your most updated copy of resume. Role: Lead ASIC DFT Engineer Work Setup: Remote, PST time zone preferred Experience Required:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep tec

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Contract, Third Party

Depends on Experience

PD Engineer

San Diego, California

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18d ago

We''re Hiring: Senior Physical Design (PD) Engineer Location: Bay Area, CA (Onsite) Experience: 8+ Years Sivaltech is looking for an experienced Senior Physical Design (PD) Engineer to join our semiconductor team. If you have expertise in advanced-node ASIC physical design and are passionate about delivering high-quality silicon, we''d love to connect with you! Key ResponsibilitiesPerform end-to-end ASIC physical design implementation from netlist to GDSII. Drive Floorplanning, Placement, Clock

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Full-time, Third Party

180,000 - 200,000

Senior MBIST Engineer

Remote

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12d ago

Business Title: Senior MBIST Engineer Location: California Job Type: Contract Note: Remote, must be working as per PST time zone Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and

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Contract, Third Party

Depends on Experience

PD Engineer

Sunnyvale, California

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2d ago

Senior Physical Design Engineer Sunnyvale, CA, USA Fulltime Visa- G C and U S C Only We are looking for a Senior Physical Design Engineer with 814 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes. This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA. What You will Do: Drive physical design flow: synthesis, floorplanning, placement, CTS, rout

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Full-time

Depends on Experience

Layout - TSMC 3n

Mountain View, California

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5d ago

Description: Seeking an experienced Analog Layout Engineer with TSMC N3 experience. Youll create high-quality, manufacturable analog layouts, collaborate with design engineers, and ensure designs meet electrical and DRC/LVS requirements. Requirements: Proven analog IC layout experience (TSMC N3 or similar) Proficiency with layout tools (Cadence Virtuoso, Synopsys, or equivalent) Strong understanding of analog performance, matching, and parasitics

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Contract

Depends on Experience

Emulation Engineer

Remote or California

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Yesterday

Senior Emulation Engineer Location: San Jose, CA (Remote) Experience: 10+ Years We are hiring an experienced Senior Emulation Engineer with strong expertise in Siemens Veloce, Cadence Palladium, or Synopsys ZeBu. Required Skills: Hands-on experience with Veloce, Palladium, or ZeBu emulation platforms Experience with FPGA prototyping (HAPS, Protium, or proFPGA) Strong knowledge of PCIe, UCIe, LPDDR, and HBM Solid understanding of SoC architecture, RTL (Verilog/SystemVerilog), and digital des

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Full-time, Part-time, Contract, Third Party

Physical Design Engineer & DV Engineers

Sunnyvale, California

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20d ago

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Lead Piping Stress Engineer 1 - Nuclear

Remote

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Today

Description Piping Engineering & Analysis Synopsis The Piping Engineering & Analysis discipline performs evaluations for piping systems in accordance with ASME Boiler and Pressure Vessel Code, ASME B31.1, ASME B31.7, and other codes as applicable to the specific evaluation being performed. The Piping Engineering & Analysis discipline also performs the following specialty topics. Vibration monitoring and analysis to evaluate system operational vibrations associated with plant modifications and

Full-time

USD 118,023.00 - 180,313.00 per year

Synopsys jobs in California, USA