timing closure jobs in remote

Immediate opening for experienced Physical Design Engineers with strong STA and timing closure experience.

San Diego, California

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23d ago

Job Title: Physical Design Engineer (STA / CTS / Floorplanning) Location: Bayarea,CA Experience: 8+ Years Employment Type: Full-Time / Contract Job Description: We are looking for a skilled Physical Design Engineer with strong experience in advanced node physical implementation. The candidate will work on RTL to GDSII implementation, timing closure, and physical verification for complex semiconductor designs. Key Responsibilities: Physical design implementation including Floorplanning, Placemen

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Full-time, Third Party

Depends on Experience

Senior STA Engineer

Remote

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10d ago

RESPONSIBILITIES - Perform static timing analysis (STA) for the PCIe subsystem within the Sparta architecture. - Develop, validate, and maintain PCIe-specific timing constraints (SDC) and exceptions. - Run fullchip and blocklevel STA for PCIe paths across PVT corners and operating modes. - Identify timing violations and drive ECO recommendations to close setup/hold, DRV, and noise issues. - Collaborate with RTL, synthesis, PnR, and verification teams to ensure endtoend PCIe timing signoff. - Ana

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Contract

80 - 90

Principal RTL Lead – High-Speed Ethernet (ASIC)

San Francisco, California

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3d ago

Principal RTL Lead High-Speed Ethernet (ASIC)Introduction:We are seeking an experienced Principal RTL Lead to drive the design and verification of next-generation Ethernet subsystems for custom ASIC silicon. This role is central to building architectures that support 400G, 800G, and beyond, enabling ultra-low latency and high reliability in large-scale data centers. As the technical lead, you will guide a team of designers through complex challenges such as multi-lane alignment, Forward Error C

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Contract, Third Party

100 - 120

Verilog Design Engineer

Remote

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27d ago

ob Title: Senior Verilog Design EngineerJob SummaryWe are looking for a Senior Verilog Design Engineer with 10+ years of experience in RTL design and digital hardware development. The ideal candidate should have strong expertise in ASIC/FPGA design flows, micro-architecture development, and SoC environments, with exposure to PCIe design or verification. Key ResponsibilitiesDevelop and implement RTL using Verilog for ASIC/FPGA platforms. Define micro-architecture and perform RTL coding, simulatio

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Contract

Depends on Experience

ASIC Implementation Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal int

Full-time

USD 141,300.00 - 226,000.00 per year

Staff Full-Chip Timing Engineer

San Jose, California

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Today

Looking for an Innovative Staff Full-Chip Timing (STA) Engineer - On Site This Jobot Job is hosted by: Lindsey Cusic Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $175,000 - $235,000 per year A bit about us: We are a growing semiconductor design organization focused on advanced ASIC and SoC development. Our team is built around deep technical expertise, fast execution, and a strong ownership mindset. We work on complex, high-performance

Full-time

USD 175,000.00 - 235,000.00 per year

PNR Applications Engineer, Staff

Sunnyvale, California

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Today

Descriptions & Requirements Job Description and Requirements We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Business Area Description: O

Full-time

Sr. FPGA Design Engineer / DSP / ASIC / Vivado IDE / Onsite / Irvine

Irvine, California

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Today

A well-established security company that helps build technology to help protect our communities. Their technology is pivotal to creating software that helps create safer schools, hospitals and ultimately a safer nation. They are currently looking for several FPGA Design Engineers. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of

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Full-time

$140000 - $200000

Engineer Digital 3

San Diego, California

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Today

Job Description Job Title: Engineer Digital 3 Location: San Diego, CA Zip Code: 92128 Duration: 6 Months Pay Rate: $54.48-$133.33/hr. Keyword's: #SanDiegojobs; #Engineerjobs. Start Date: Immediate Job Description: Responsibilities: * Design, develop, integrate and test VHDL-based digital designs for our end-user customers and businesses, primarily focused on software defined radio VHDL firmware code bases. * Work using FPGA programming development tools and environments * Work with multi-discip

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Full-time

Compensation information provided in the description

Sr Principal Application Engineer

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Summary The Senior Principal Application Engineer will be a trusted technical leader, driving complex pre-sales and post-sales engagements for Cadence Digital IC products at advanced nodes. This role demands a proven ability to solve the toughest design challenges and deliver innovative solutions that ensure customer success. Key Responsibilities Lead technical strateg

Full-time

USD 143,500.00 - 266,500.00 per year

Emulation Methodology Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. Qualcomm's Emulation Team is part of the central SoC digital hardware organization responsible for the overall development and support of SoC

Full-time

USD 140,000.00 - 210,000.00 per year

Engineer Digital 3

San Diego, California

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Today

Location: San Diego, CA Salary: $80.00 USD Hourly - $125.00 USD Hourly Description: Position: Digital Engineer (FPGA / VHDL) Location: San Diego, CA About the Role We are seeking a Digital Engineer to join a mission-focused engineering team working on advanced digital systems. In this role, you will design, develop, integrate, and test FPGA-based solutions that support next-generation, software-defined radio and communication systems. You will collaborate closely with cross-functional engine

Contract

Compensation information provided in the description

Application Engineer Architect

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview The Architect will serve as a technical leader within Cadence's North America Field Applications Team, driving strategic customer engagements and influencing next-generation EDA & Agentic-AI solutions. This role demands exceptional technical depth, hands-on experience of design convergence, and the ability to align cross-functional teams toward delivering advanced design solut

Full-time

USD 157,500.00 - 292,500.00 per year

Application Engineer, RTL2GDS Architect

San Jose, California

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Today

Full-time

USD 157,500.00 - 292,500.00 per year

Principal STA Engineer

Austin, Texas

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Today

Full-time

ASIC Design Engineer

Atlanta, Georgia

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Today

Leading semiconductor manufacturer with competitive compensation, generous bonus, and stock options! Also offering relocation bonus and/or be willing to relocate to Atlanta, GA This Jobot Job is hosted by: Michael Ramsey Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $125,000 - $200,000 per year A bit about us: Leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center mark

Full-time

USD 125,000.00 - 200,000.00 per year

Senior Electrical Engineer - ASIC/FPGA Mission Systems (Onsite)

El Segundo, California

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Today

Date Posted: 2026-03-05 Country: United States of America Location: US-CA-EL SEGUNDO-E01 ~ 2000 E El Segundo Blvd ~ BLDG E01 Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: Active and transferable U.S. government issued security clearance is required prior to start date.Security Clearance Type: DoD Clearance: Secret Security Clearance Status: Active and existing security clearance required on day 1 Joining Collins Aerospace isn't just about finding a

Full-time

USD 95,500.00 per year

Senior Staff Engineer, Physical Implementation CAD Lead

Austin, Texas

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Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 180,200.00 - 297,200.00 per year

Senior FPGA Engineer (Onsite)

Cedar Rapids, Iowa

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Today

Date Posted: 2026-02-12 Country: United States of America Location: US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtain and maintain a U.S. government issued security clearance is required.Security Clearance Type: DoD Clearance: Secret Security Clearance Status: Active and existing security clearance required after day 1 Joining Collins Aerospace isn't just about finding a job; it's

Full-time

USD 86,800.00 per year

FPGA Engineer - P4- Cleared On-Site

Tucson, Arizona

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Today

Job#: 3023981 Job Description: **Candidates must be able to obtain and/or maintain a Department of Defense Secret Security Clearance as a condition and continuation of employment** Senior FPGA/ASIC Design or Verification Engineer Work Schedule: 9/80 Location: Onsite Education: Bachelor's degree in Electrical or Computer Engineering Experience Level: Senior (8+ years) Overview We are seeking a Senior FPGA/ASIC Design or Verification Engineer to support advanced digital hardware development

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Full-time

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timing closure jobs in remote