Uvm jobs in phoenix, az

Chandler, Arizona

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Today

Job Description: Duties: Perform semiconductor engineering design, development, and testing for firm products and devices in conjunction with product development for the electronic communications industry. Participate in the digital functional verification of NXP's mixed-signal circuit designs. Responsible for developing the UVM simulation environment (drivers, monitors, checkers, and assertions) and bridge with mixed signal verification. Develop and run digital and top-level simulations accordi

Full-time

USD 174,070.00 per year

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions

Scottsdale, Arizona

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Today

Basic Qualifications Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience. CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified

Full-time

USD 135,396.00 - 150,205.00 per year

Principal Analog Mixed Signal Verification Engineer

Chandler, Arizona

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Today

Job Title: Principal Analog Mixed-Signal Verification Engineer Primary Location: Chandler, Arizona, USA Role Summary: Lead analog and mixed-signal verification for automotive and industrial PMIC products from specification through verification signoff.Define verification strategies, environments, regressions, and coverage objectives for complex mixed-signal IPs, subsystems, and SoCs.Collaborate with cross-functional teams to ensure product quality, reliability, functional correctness, safety,

Full-time

Principal Digital Verification Engineer

Chandler, Arizona

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Today

Job Title: Principal Digital Verification Engineer Primary Location: Chandler, Arizona, USA Role Summary: The Advanced Power Systems group within NXP's Power and Energy Business Line is seeking a Senior Digital Verification Engineer to develop next-generation Power Management ICs (PMICs) for automotive and industrial applications. This role will lead digital verification from architecture review through verification signoff, ensuring functionality, quality, reliability, and compliance. Job Re

Full-time

Design Verification Engineer

Remote

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Today

Hi, Job Title: Design Verification Engineer Location : Remote USA Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols. Thanks & Regards.., Arun Prasath Reveille Technologies, Inc

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Third Party, Contract

Depends on Experience

SoC verification Engineer

Remote

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Today

Position : SoC verification Engineer Location : Remote Must Requirement : End-to-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.) Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end-to-end UVM expertise. Key Responsibilities Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off.Testbench & Component Devel

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Contract

$70+

SoC Verification Specialist

Remote

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Today

Must Requirement : End-to-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.) Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end-to-end UVM expertise. Key Responsibilities Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off.Testbench & Component Development: Build and maintain verification components, te

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Contract

Depends on Experience

SoC Design Verification Engineer

Remote

•

Today

Responsible for SoC level verification, driving verification execution, integration, coverage closure, low-power verification, GLS, and test-chip validation activities. Key Responsibilities 1. Develop and execute SoC-level verification plans, testcases, and coverage models to validate subsystem interactions, system functionality, and integration requirements. 2. Integrate IPs, UVCs, and VIPs into the SoC verification environment. 3. Drive functional/code coverage closure, power-aware verificati

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Contract

Depends on Experience

SoC Verification Engineer

Remote

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2d ago

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Contract, Third Party

60 - 70

DV IP Design Verification Engineer

Remote

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Yesterday

Position: DV IP Design Verification Engineer Location: Remote Employment Type: Contract Job SummaryWe are looking for an experienced Design Verification Engineer with strong expertise in IP/Block-level verification to support verification of complex digital IPs. The ideal candidate will have hands-on experience developing SystemVerilog/UVM-based verification environments, creating verification plans and testcases, debugging RTL and testbench issues, and driving functional/code coverage to closur

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Contract

Depends on Experience

DV SOC / SoC Design Verification Engineer

Remote

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Yesterday

Position: DV SOC / SoC Design Verification Engineer Location: Remote Job Type: Contract Job SummaryWe are looking for an experienced SoC Design Verification Engineer to support SoC-level verification, integration, and signoff activities for complex ASIC/SoC designs. The ideal candidate will have strong hands-on experience with SystemVerilog, UVM, SoC verification, RAL, low-power verification using UPF, Gate-Level Simulation (GLS), and coverage closure. This role will involve integrating IPs/UVCs

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Contract

Depends on Experience

Manager, Infrastructure Governance

Remote or Ohio

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Today

What Infrastructure Governance contributes to Cardinal Health Information Technology oversees the effective development, delivery, and operation of computing and information services. This function anticipates, plans, and delivers Information Technology solutions and strategies that enable operations and drive business value. Infrastructure Governance enforces Cardinal Health's risk and security policies to ensure compliance with internal and external regulations, and to maintain a secure infr

Full-time

USD 125,300.00 - 178,900.00 per year

Analog Mixed Signal Modeling Engineer (UL - 02)

Chandler, Arizona

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Today

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn't do it without our extraordinary workforce

Full-time

Design Engineer II # 26-23166

Remote

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11d ago

Duration: 8 Months Contract Summary: A contract digital design engineer to own integration of the camera ingest path MIPI C/DPHY and CSI2 receivers into the image signal processing (ISP) pipeline including development of the glue logic required to bridge CSI2 and ISP interfaces. Duties:Integrate MIPI CPHY/DPHY, CSI2 controller and ISP IPs at subsystem and chip levelDesign and code the glue logic between CSI2 output and ISP input: stream/virtualchannel handling, datatype unpacking, line/frame

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Contract

$70 - $150

Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)

Scottsdale, Arizona

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Today

Basic Qualifications Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience. Clearance Requirements: Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subj

Full-time

USD 122,785.00 - 136,215.00 per year

Design Engineer II # 26-23167

Remote

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11d ago

Duration: 8 Months Contract Summary: Overview Contract digital design engineer to integrate the lowspeed peripheral subsystem I3C, I2C, SPI/QSPI/OSPI, UART controllers including the IO cells, pad ring connectivity and IO multiplexing that these peripherals depend on. Duties Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top Own IOlevel integration: pad/IO cell selection and configuration, IO mux design and programmability, pullup/pulldown, drive

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Contract

$70 - $150

Principal Product Engineer - Virtual Protocols

Remote or San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Business Overview Deliver Emulation and Prototyping assisted verification products using virtualization (SW) technologies to accelerate and shift left SW-driven pre-silicon verification of advanced SoC designs. Job Description This Principal Product Engineer position is with the Virtual Protocols Product Engineering Team, responsible for the successful field readiness and customer dep

Full-time

USD 136,500.00 - 253,500.00 per year

Staff Engineer, Design Verification Engineering

Chandler, Arizona

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Today

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI

Full-time

USD 172,390.00 - 199,229.00 per year

Senior SoC Verification Engineer

Remote

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3d ago

Role: SoC Verification Work Location: Remote 100% Duration: Long Term Implementation Partner - HCL America Key Responsibilities Block-Level Verification Ownership:Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off. Testbench & Component Development:Build and maintain verification components, test sequences, agents, scoreboards, and functional coverage models from scratch usingSystemVerilog and UVM. Verification Execution:

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Contract

Depends on Experience

Uvm jobs in Phoenix, AZ, USA