Key Responsibilities: IP Integration: Develop wrappers for IPs to build integrated SoC systems on FPGA. Porting & Adaptation: Port wrappers and logic across different configurations and hardware platforms. Bitstream Generation: Manage the end-to-end flow from synthesis to bitfile generation and flashing onto HW. System Testing: Conduct functional testing of the FPGA bitfile and overall hardware system. HW Debugging: Perform deep-dive debug using on-chip logic analyzers (ILA/SignalTap) and JTAG.