Strong experience in Digital Design Verification (DV) with exposure to TI (Texas Instruments) projects preferred Proficiency in SystemVerilog for verification environments Hands-on experience in digital verification methodologies and testbench development Familiarity with mixed-signal designs, preferably involving ADC-based chips Experience working in Unix/Linux environments Hands-on experience with Cadence Xcelium simulation tool Comfortable working with both Linux/Unix and Windows-based enviro