Remote
•
Today
5+ years of digital front-end / RTL design experienceExperience integrating CPU cores, bus architectures, and peripheral IPs into SoC or ASIC designsWorking knowledge of ARM AMBA protocols AXI / AHB / APB(Assumption: viewed as a strong plus please let me know if this should be mandatory) Strong subsystem-level integration and debug skillsProficiency in Verilog / SystemVerilog
Easy Apply
Third Party, Contract
Depends on Experience

