Job Description: RESPONSIBILITIES - Perform static timing analysis (STA) for the PCIe subsystem within the Sparta architecture. - Develop, validate, and maintain PCIe-specific timing constraints (SDC) and exceptions. - Run fullchip and blocklevel STA for PCIe paths across PVT corners and operating modes. - Identify timing violations and drive ECO recommendations to close setup/hold, DRV, and noise issues. - Collaborate with RTL, synthesis, PnR, and verification teams to ensure endtoend PCIe timi