SystemC Modelling Engineer We are hiring a SystemC Modelling Engineer with strong experience in virtual platform development and transaction-level modeling for embedded/SoC systems. Core Skills SystemC, TLM, C++ (OOP) HDLs: VHDL / Verilog Simulation: Cadence Incisive, Synopsys VCS, QuestaSim Debugging: GDB, DVE Python/Perl scripting, Git Embedded architecture (CPU, memory, bus protocols) Key Responsibilities Develop TLMs for interfaces (I2C, SPI, USB, CAN, Ethernet) Build virtual prototypes & sy