Company Description We are seeking a Senior Analog Engineering Manager to lead the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs. This role requires deep technical expertise in high-speed memory interfaces, combined with strong people leadership and program ownership. The successful candidate will manage a team responsible for end-to-end delivery of high-performance, low-power DDR PHYs, from architecture through silicon bring-up, while shaping the roadmap for DDR