Mixed Signal Model Verification Engineer Hybrid Role in San Jose, CA 3 Months MUST HAVE SKILLS: Extensive experience in modeling mixed signal circuits in SystemVerilog, including real number modeling Strong understanding of HDL/SPICE co-simulations Strong understanding of custom circuit schematic Strong background in analog integrated circuit design Proficiency in RTL design languages like SystemVerilog Experience with formal equivalence checking tools like ESP We are seeking a detail-oriented