Physical Design Engineer San Jose, CA (onsite) Long Term Contact Strong experience in RTL synthesis using Cadence GenFusion compiler, including SDC constraint development and QoR optimization (timing, area, power) Hands-on expertise in Static Timing Analysis using Tempus, including setup/hold closure, C scenarios, OCV, and timing signoff concepts Ability to analyze and debug timing violations across synthesis and floorplan stages and drive closure Experience in block-level floorplanning using Ca