Job Description Senior Staff Engineer, Digital Verification San Jose, CA Onsite Requirements: Bachelors with 15+ years of relevant industry experience, or Masters with 13+ years or PhD with 10+ years in Electrical Engineering or related field preferred. Experience in developing test benches using SystemVerilog UVM, testcase development skills for constrained random and directed scenarios Experience in MCU/CPU Verification at processor level and at sub-system level both. a. Strong understanding