Role: Staff Physical Design Engineer Top-Level Timing & STA Location - San Jose, CA Work Type: Onsite 5 Days Job Type: C2C Experience: Total 8+ years Relevant -5 + Years About the job We are looking for a Senior/Staff STA Engineer to lead full-chip timing signoff activities for cutting-edge SoCs at advanced technology nodes (5nm / 3nm / 2nm). The candidate should possess deep expertise in C timing closure, hierarchical timing budgeting, ECO convergence, and final tapeout signoff. This role re