DFT Engineer – Scan / ATPG / MBIST
Location: Santa Clara, CA (Bay Area)
Position: DFT Engineer
Work Arrangement: Onsite/Hybrid as per project requirements
Job Summary
We are seeking a skilled Design for Test (DFT) Engineer to join our semiconductor engineering team in Santa Clara, California. The ideal candidate will have hands-on experience with DFT methodologies, with strong knowledge of Scan, ATPG, and MBIST.
The candidate will be responsible for implementing, validating, and debugging DFT solutions across the ASIC/SoC development lifecycle while working closely with RTL, Design, Verification, Physical Design, and Silicon Validation teams.
Key Responsibilities
Develop and implement DFT architectures and methodologies for ASIC/SoC designs.
Design and integrate Scan-based DFT structures.
Develop and validate ATPG (Automatic Test Pattern Generation) solutions.
Implement and debug MBIST (Memory Built-In Self-Test) architectures for embedded memories.
Analyze and improve fault coverage, test quality, and testability.
Generate, validate, and debug scan/ATPG patterns.
Perform DFT rule checks, coverage analysis, and pattern simulations.
Debug DFT-related failures at RTL, gate-level, and post-silicon stages.
Collaborate with RTL and design teams to resolve DFT insertion and testability issues.
Work with physical design teams to ensure successful implementation of DFT structures.
Analyze ATPG reports and identify coverage gaps and test pattern issues.
Support scan chain development, stitching, balancing, and debugging.
Validate MBIST controllers, memory test sequences, and associated logic.
Support test pattern generation, simulation, and silicon bring-up activities.
Document DFT implementation, test methodologies, debug results, and project status.
Required Skills
Strong understanding of Design for Test (DFT) concepts and methodologies.
Hands-on experience with Scan architecture and implementation.
Strong experience with ATPG and test pattern generation.
Experience with MBIST implementation and validation.
Understanding of ASIC/SoC design and verification flows.
Experience debugging DFT issues across RTL and gate-level designs.
Knowledge of fault models and fault coverage analysis.
Understanding of scan chains, scan compression, test modes, and test clocks.
Strong problem-solving and debugging skills.
Ability to work effectively with cross-functional semiconductor engineering teams.
Preferred Skills
Experience with DFT insertion and verification tools.
Knowledge of scan compression and EDT methodologies.
Experience with JTAG / IEEE 1149.1.
Knowledge of IEEE 1500 or other test standards.
Experience with memory testing and MBIST controllers.
Experience with boundary scan.
Familiarity with RTL, Verilog/SystemVerilog, synthesis, and gate-level simulation.
Experience with DFT-related scripting and automation using Tcl, Python, or Perl.
Exposure to physical design and timing considerations for DFT.
Experience with silicon bring-up and post-silicon DFT debug.
Ideal Candidate
The ideal candidate will be a DFT Engineer with strong hands-on experience in Scan, ATPG, and MBIST, capable of working across the ASIC/SoC development lifecycle. Strong DFT expertise is highly desirable, with the ability to collaborate with design, verification, physical design, and validation teams.
Primary Skills:
DFT | Scan | ATPG | MBIST | ASIC/SoC | Test Coverage | DFT Debug
Location: Santa Clara, CA (Bay Area)
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