DFT Engineer

Title: DFT Engineer Location: Santa Clara, CA Role Purpose We are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary Scan Key Responsibilities: Work on Scan insertion, ATPG, GLS (timing/non-timing)Implement MBIST and/or Boundary Scan (BSCAN, JTAG)Support DFT architecture and chip-level integrationDebug DFT issues and improve test coverage Requirements: Experience in at least 2 DFT areas (Scan/ATPG/MBIST/BSCAN/GLS)Strong understanding of DFT concepts and flowExposu

Required Skills & Qualifications: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs. Strong understanding of DFT fundamentals, including controllability, observability, and scan-based testing. Proven expertise in ATPG pattern generation, analysis, and debug. Experience with MBIST, including memory test architectures and diagnostics. Knowledge of IO test methodologies for interface- and pin-level validation. Solid understanding of clock DFT and clock verification concepts. S

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Required Skills & Qualifications 4+ years of hands-on experience in DFT and ATPGfor SoC or ASIC designsStrong understanding of DFT fundamentalsincluding controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Tes

We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team.In this role, you will be responsible for designing and implementing Design-for-Test (DFT) solutions that ensure high manufacturing quality, test coverage, and efficient production testing for complex semiconductor devices.Key ResponsibilitiesDesign and implement DFT architecture for ASIC and SoC designs.Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.Perform ATPG, fault