CPU DFT Verification Engineer

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product!\\n\\nWe are looking for a strong candidate to join our processor verification team focusing on DFT verification. In this highly visible role, you will be at the center of a chip design effort collaborating with all subject areas, with a critical impact on getting functional products to millions of customers quickly.

As a CPU DFT Verification Engineer, you will have the following responsibilities:\n\n Work closely with architecture, RTL designers, and DFT designers on verifying the functionality correctness of the DFT logic\n Execute test plans for DFT logic\n Develop testbenches and tests according to test plans\n Debug simulation failures\n Develop coverage monitors and analyze coverage to ensure all test cases in the plans are covered\n Develop Verilog checkers or assertions to verify the design\n Work with the silicon bringup team on developing tests that help the silicon bring up effort

Minimum BS and 3+ years of relevant industry experience\nExperience in DFT design, DFT verification, or processor verification\nExperience with digital logic design, test/debug feature, or DFT architecture\nExperience with DFT and structural debug concepts and methodologies: JTAG, IEEE1500, or MBIST and scan\nExperience in scripting in Python, Perl, or TCL

Master's degree preferred\nUnderstanding of CPU architecture\nExperience in developing design verification test plans, test benches, and test vectors generation\nExperience with lab debug of CPASIC using built-in DFT and debug features is a plus\nIn-depth knowledge in design verification environments like random constraint verification\nKnowledge of Verilog and experience with simulators and waveform debugging tools\nShould be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort\nBe able to create and follow detailed work schedule and work independently on the verification efforts for a block/area of the design