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Hiring DFT Engineer in Santa Clara CA | Hybrid | FTE/Contract

Santa Clarita, California

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Today

Hi, Please check the below job DFT Engineer Location: Santa Clara, CA (Hybrid 3 Days Onsite) Employment Type: Full-Time / W2 Contract Experience: 3 12 Years Industry: Semiconductor / VLSI / ASIC Design Job Overview We are seeking a highly motivated DFT (Design for Test) Engineer to join a fast-growing semiconductor team developing next-generation SoCs and ASICs. The ideal candidate will be responsible for architecting, implementing, and validating DFT solutions for complex designs at advanced

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Full-time, Contract

Lead ASIC DFT Engineer - W2 role - Remote

Remote

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Today

Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution o

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Contract

Depends on Experience

DFT Engineer

Remote

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7d ago

Contract role. 12 months Remote 3 Main priorities below: 1- Tile Based Approach 2-TessentSSN- specificallySSN 3- MCM Packages/Die-To-Die ChipsDFT engineer- Expert with Tessent tools. Experience with TessentSSN. Experience working on ATPG, MBIST, JTAG,DFTInsertion. Experience with ownDFTVerification. Experience with ICL PDL.

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Contract, Third Party

60 - 90

Lead ASIC DFT Engineer

Remote

•

Today

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation,

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Contract

$50 - $60

Senior DFT Engineer

Remote

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Today

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep

Full-time

USD 170,000.00 - 250,000.00 per year

Principal Test Engineer/DFT Architect

Remote or Austin, Texas

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Today

Company Description The Principal Test / DFT Architect will define testability and production test strategy for advanced semiconductor products from concept through production release. This role bridges ATE test architecture, DFT, circuit design, product engineering, validation, quality, operations, and manufacturing to ensure products are designed for high-quality, cost-effective, scalable production test. The ideal candidate has deep semiconductor ATE test experience, strong knowledge of ana

Full-time

ASIC DFT Engineer

Remote

•

Today

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, a

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Contract, Third Party

Depends on Experience

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