FPGA / RTL Design Engineer

VARITE is looking for a qualified FPGA / RTL Design Engineer in San Jose, CA WHAT THE CLIENT DOES? A major multinational conglomerate, commanding leadership in Engineering, Procurement, and Construction (EPC) projects, Hi-Tech Manufacturing, and Services. As of 20242025, it is a $2730 billion USD entity operating in over 50 countries. It is often considered an industrial backbone, involved in critical, large-scale nation-building projects. WHAT WE DO? Established in the Year 2000, VARITE is an

Title: RTL Design Engineer - Onsite Mandatory skills: FPGA, design, simulation, synthesis, implementation, Vivado, TCL, Python coding, product development cycle, implementation, prototyping, validation, productization, support, architecture, design, documentation, RTL Developmen, verify, high-performance logic, System Verilog/Verilog, data, control path, implementing interfaces, PCIe, Gen 6, Gen 7, CXL, UAL, Ethernet, DDR5, DDR6, integrate custom IP, Network on Chip, NoC, Memory, subsystems Desc

Role: RTL Engineer, Location: Dallas, Texas Work Mode: Onsite Contract Duration: 6 Months, Job Description: We are currently seeking a highly skilled RTL/ASIC Design Engineer to join our dynamic team. If you possess hands-on experience and expert-level knowledge in RTL design, SoC integration of ARM core-based designs, and a deep understanding of Verilog/VHDL, we invite you to apply. Responsibilities: Execute RTL design and coding with expert-level proficiency Integrate ARM core-based designs i

Role: RTL Engineer Location: Santa Clara CA Required Skills and Qualifications: Education: Bachelor's or master s degree in electrical engineering, Computer Science, or a related field. Experience: Proven experience in RTL design and integration (using Verilog, VHDL, or SystemVerilog). ARM core based design experience, ARM SMMU design exposure and Python experience. Hands-on experience with digital design verification and subsystem integration. Experience with quality assurance tools and process