Verilog Design Engineer

Senior FPGA Architect / Principal FPGA Engineer - Real-Time Processing Systems Architect-level FPGA expertise designing high-performance real-time processing systems and complex programmable logic architectures. Advanced RTL development using Verilog / SystemVerilog for high-throughput pipelines, accelerators, and timing-sensitive hardware logic. Experience building FPGA-based SoC architectures including AXI/Avalon fabrics, DMA engines, memory controllers, and multi-clock domain designs. St

RequirementsKnowledge of semiconductor ASIC design/verification methodologies and flows Working knowledge of Verilog/SystemVerilog/UVM Strong programming skills including object-oriented programming Working experience with digital logic design and verification Practical experience in D2D, NOC, AXI, Ethernet, DDR/LPDDR, HBM, Security, Networking, ARM CPU subsystems Demonstrates good analysis, problem-solving, and critical thinking skills Effective interpersonal, teamwork, and communication skills

Date Posted: 2026-01-28 Country: United States of America Location: US-UT-SALT LAKE CITY-547 ~ 600 Komas Dr ~ KOMAS Position Role Type: Hybrid U.S. Citizen, U.S. Person, or Immigration Status Requirements: This job requires a U.S. Person. A U.S. Person is a lawful permanent resident as defined in 8 U.S.C. 1101(a)(20) or who is a protected individual as defined by 8 U.S.C. 1324b(a)(3). U.S. citizens, U.S. nationals, U.S. permanent residents, or individuals granted refugee or asylee status in the

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi