Position: Physical Design Engineer
Location: Remote
Time Zone: CST
Focus: Physical Design | Place & Route (PnR) | PPA Optimization | Timing Closure
Key Responsibilities
- Drive block-level physical design implementation from netlist to GDSII.
- Perform floorplanning, power planning, placement, CTS, routing, and physical verification.
- Optimize designs for Power, Performance, and Area (PPA).
- Achieve timing closure across multiple modes and corners.
- Analyze and resolve setup, hold, transition, capacitance, and noise violations.
- Develop and maintain SDC timing constraints and support STA signoff methodologies.
- Perform EMIR (Electromigration and IR Drop) analysis and closure.
- Collaborate with RTL, DFT, STA, and Signoff teams to support successful tapeout.
- Debug physical design issues and drive design convergence.
Required Skills
Physical Design | PnR | Floorplanning | Power Planning | Placement | Optimization | CTS | Routing | Timing Closure | STA | SDC | EMIR | PPA Optimization | Physical Verification | Signoff
EDA Tools
Synopsys Fusion Compiler | Synopsys ICC2 | Synopsys PrimeTime | Cadence Innovus | RedHawk | Voltus
Preferred Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field.
- Experience with advanced nodes, preferably 7nm / 5nm / 3nm.
- Strong debugging, analytical, and problem-solving skills.
- Experience working with cross-functional RTL, DFT, STA, Signoff, and Silicon Engineering teams.
- Good understanding of low-power design and signoff methodologies.
Candidate Profile
Looking for candidates with hands-on Physical Design / PnR experience, including floorplanning, placement, CTS, routing, timing closure, STA, SDC, EMIR, PPA optimization, and physical design signoff.
Please share an updated resume highlighting hands-on Physical Design/PnR, timing closure, advanced-node experience, and EDA tool expertise.
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