Senior ASIC DFT CDC Constraints Eng

Job Title: ASIC Engineering Technical LeaderLocation: RemoteDuration: 12+ month ContractJOB DESCRIPTION:Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing)methodology in silicon one chips Design & implement robust and reusable RTL with CDC/RDC considerations Spec comprehensive CDC/RDC check flows and work with CAD team to implement Review and approve CDC/RDC constraints and waivers Perform static glitch analysisImprove design with prevention of static glitch harzad Bachelor''s or Ma

R-069895 RTL Design Engineer Wireless SoC (Remote PST) Location: Remote (must be aligned with PST time zone / willing to work PST hours) We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon. Required Skills 5+ years of hands-on RTL design experience (

RTL Design Engineer Key Responsibilities Own micro-architecture definition from high-level functional specificationsDevelop and implement RTL for complex digital blocksDrive digital block control and IP integrationParticipate in subsystem-level architecture alignmentSupport design sign-off activities (CDC, RDC, lint, synthesis readiness)Collaborate closely with DV for closure and debugRequired Qualifications Strong expertise in RTL design (SystemVerilog/Verilog)Experience defining micro-architec

Location:REMOTEDuration: ~12 months (Immediate start through Q1 next year)Team Size: ~10 Engineers (Mix ofDesign & DV )Question from hiring manager on prior submital: Can you also check with the candidates on their recent hands-on experience with RTL design using SystemVerilog, & working on IPs with multiple clock domains?1. RTLDesignEngineerKey ResponsibilitiesOwn micro-architecture definition from high-level functional specificationsDevelop and implement RTL for complex digital blocksDrive dig