Senior Design Verification Engineer

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

RequirementsKnowledge of semiconductor ASIC design/verification methodologies and flows Working knowledge of Verilog/SystemVerilog/UVM Strong programming skills including object-oriented programming Working experience with digital logic design and verification Practical experience in D2D, NOC, AXI, Ethernet, DDR/LPDDR, HBM, Security, Networking, ARM CPU subsystems Demonstrates good analysis, problem-solving, and critical thinking skills Effective interpersonal, teamwork, and communication skills