Sr. Design for Test Engineer

Role: Sr. Design for Test Engineer Duration: 12 months Location: Remote Role Industry: Need candidate who have 2-3 years of experience with Semiconductor industry Required: 5 - 7 years of experience in DFT.Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing).MBIST Insertion and Verification.Experience in I 1149.1 JTAG Insertion and verification.Scripting languages like Perl, Shell, and TCL.Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various I

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation,

Title: Lead ASIC DFT Engineer Remote (must be aligned with PST time zone) Job Type: Contract Key skills for Lead ASIC DFT: SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC, PSV, Diagnosys, Pattern Retargeting, Pattern porting, DRCs, TetraMax, DFTMax Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs

Job Title: Lead ASIC DFT EngineerLocation: Remote (PST time zone)Duration: 12 Months Key skills for Lead ASIC DFT: SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary:We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This