Sr. Design for Test Engineer for W2

Job Summary (Sr. Design for Test Engineer) - Minimum 57+ years of DFT (Design for Test) experience, including Scan Insertion, ATPG, MBIST, and JTAG (I 1149.1) Insertion & Verification. - 23 years of recent experience in the semiconductor industry is required. - Proficient in DFT implementation for advanced nodes (3nm/5nm), targeting Networking chips and IP blocks (including PLL and SerDes). - Hands-on expertise in Mentor Tessent, Cadence Modus, Synopsys Tetramax, and VCS simulation tools.

Title: Lead ASIC DFT Engineer Remote (must be aligned with PST time zone) Job Type: Contract Key skills for Lead ASIC DFT: SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC, PSV, Diagnosys, Pattern Retargeting, Pattern porting, DRCs, TetraMax, DFTMax Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs

Job Title: Lead ASIC DFT EngineerLocation: Remote (PST time zone)Duration: 12 Months Key skills for Lead ASIC DFT: SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary:We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This

Position: Senior DFT Engineer (Einfochips) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT workRTL checks for scan-insertion compatibility using Synopsys SpyglassScan-Insertion using Tessent TestKompressATPG pattern generation:Compressed and Uncompressed ModeTools: Mentor Tessent, Cadence Modus & Synopsys TetramaxPattern Simulation:Without timing, With timing for different cornersTools: VCSMismatch debug using VerdiScripting with Perl, Shell, T