Physical Design Engineer

Job Title: Physical Design Engineer Location: San Jose CA Contract We are seeking a Physical Design contractor with strong synthesis and implementationexpertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designsDrive PPA (power, performance, area) optimization through synthesis and earlyimplementation stages. Develop and refine floorplans using Cadence InnovusCollaborate c

Position:Physical Design Engineer II (IC) Job Description:What candidate will Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.Partner with the design team to proactively ide

Descriptions & Requirements Job Description and Requirements We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You A

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y