Role :- Senior ASIC DFT CDC Constraints Eng
Location :-
San Jose, CA/Milpitas, CA (Remote) Type :- */W2
This is a highly specialised role at the intersection of Design for Test (DFT) architecture and clock domain crossing (CDC) constraint engineering. The successful candidate will own the SDC/SSTA constraint strategy that governs both functional timing closure and DFT scan-mode operation across a complex multi-clock SoC. You will work daily at the boundary where CDC violations manifest as scan-shift failures and at-speed test escapes — a problem space that demands simultaneous mastery of CDC theory, ATPG methodology, and STA constraints.
This role requires candidates who understand why CDC synchronizers must be de-rated or bypassed in scan mode, and how incorrect set_false_path / set_multicycle_path constraints can both mask real timing violations and cause false DRC failures during ATPG.
CDC constraint ownership - Author and maintain all SDC constraints governing CDC paths and multicycle paths across asynchronous clock groups
- Validate coverage against the clock architecture document
- Ensure CDC synchronizer cells (2FF, pulse sync, async FIFO) are correctly modelled in SDC so STA neither over-constrains nor under-constrains the settling window
- Own the netlist-level CDC constraint audit at each design milestone (RTL freeze, post-synthesis, post-PnR)
- Coordinate with CDC signoff (SpyGlass / JasperGold) and STA (PrimeTime / Tempus) teams to ensure constraint consistency between tools
DFT & scan-mode constraints - Develop DFT-specific SDC views: scan-shift mode, scan-capture mode, and at-speed (LBIST / ATPG) constraint sets
- Resolve conflicts between functional CDC false-paths and scan-path connectivity — ensure scan chains do not inadvertently create new CDC violations or bypass synchronizers
- Define clock controller constraints during test mode: mux-select overrides, scan-enable timing, and test-clock relationships
- Work with ATPG engineers (Tessent / Synopsys DFTC) to validate that test patterns respect CDC-related timing exceptions and do not produce X-propagation from uncontrolled CDC paths
- Support fault simulation and at-speed test coverage analysis for paths crossing clock domains
Additional responsibilities - Drive constraint convergence through place-and-route iterations; work with PnR team to resolve CDC-related hold violations introduced by synchronizer placement
- Develop and maintain internal SDC constraint guidelines, naming conventions, and waiver documentation for CDC exceptions
- Review third-party IP CDC constraint packages; identify gaps and define interface constraints at IP boundaries
- Contribute to sign-off checklist and tapeout readiness reviews for timing and DFT closure
- Mentor mid-level engineers on CDC-aware constraint methodology and scan-mode timing analysis
- Engage with EDA vendors (Synopsys, Cadence, Siemens EDA) on tool limitations affecting CDC constraint modelling in scan mode
Required qualifications CDC & STA expertise - 10+ years in ASIC/SoC with 5+ years in SDC constraint development and STA sign-off
- Deep understanding of CDC synchronization structures and their correct constraint representation in SDC
- Hands-on with PrimeTime, Tempus, or Fusion Compiler for timing analysis
- Proficient in SpyGlass CDC or JasperGold CDC for structural CDC analysis
- Strong grasp of metastability, MTBF, and synchronizer settling time budgets
- Experience constraining Gray-code FIFO pointers and pulse synchronizers across tool flows
DFT expertise - Solid understanding of scan insertion, scan chain stitching, and ATPG flow
- Experience authoring DFT-mode SDC views (shift / capture / at-speed)
- Familiarity with Tessent (Siemens) or Synopsys DFTC ATPG toolchain
- Able to debug X-propagation issues in scan mode arising from unconstrained CDC paths
- Understanding of LBIST clock generation and its interaction with functional CDC clocks
Preferred qualifications - Experience with advanced nodes (7nm, 5nm, 3nm) where synchronizer hold margins are critically tight
- Familiarity with IEEE 1500 / 1687 (IJTAG) and their clock domain implications in embedded instruments
- Background in safety-critical design (ISO 26262 ASIL-B/D) and associated DFT diagnostic coverage requirements for CDC paths
- Knowledge of MBIST and its interaction with functional clock domains during test
- Scripting proficiency in Tcl and Python for constraint generation, audit, and regression automation
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or equivalent
Key deliverables owned by this role - Master SDC constraint set (functional + DFT modes)
- CDC constraint sign-off at each tape-out milestone
- DFT X-propagation debug for CDC paths
- CDC constraint guidelines & waiver policy
- IP boundary constraint reviews
- Constraint regression automation scripts
About Tanisha Systems, Inc. Tanisha Systems, founded in 2002 in Massachusetts-*, is a leading provider of Custom Application Development and end-to-end IT Services to clients globally. We use a client-centric engagement model that combines local on-site and off-site resources with the cost, global expertise and quality advantages of off-shore operations. We deliver Custom Application Development, Application Modernization, Business Process Outsourcing and Professional IT Services from office locations in * and *.
Tanisha Systems services clients in Government, Banking & Financial Markets, Insurance, Healthcare, Retail & Consumer Goods, Energy & Utilities, Life Sciences, Telecom, Manufacturing and Transportation Industries around the globe. Our engagement model provides a flexible operational environment that empowers our clients with the right levels of control.
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