Hi,
Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification]
Location : Santa Clara, CA
Experience : 4+ Years in DFT
Job Summary
We are seeking an experienced Senior DFT / ATPG Engineer to support client s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engineer will work closely with client crossfunctional teams to enable firsttimeright silicon and highquality products.
Required Skills & Qualifications
- 4+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs
- Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing
- Proven expertise in ATPG pattern generation, analysis, and debug
- Experience with MBIST, including memory test architectures and diagnostics
- Knowledge of IO Test methodologies for interface and pinlevel validation
- Solid understanding of clock DFT and clock verification concepts
- Strong grasp of digital design and RTL fundamentals
- Experience with industrystandard DFT/ATPG EDA tools
- Ability to work effectively in fastpaced, highperformance semiconductor programs
- Strong analytical, problemsolving, and communication skills
Preferred Qualifications
- B-Tech , BE or equivalent degree in Electronics domain.
- Experience with silicon bring-up and production test support
- Exposure to advanced nodes and complex SoC & GPU architectures
- Exposure to lowpower and performanceaware DFT techniques
- Experience supporting highvolume production and yield optimization
- Knowledge of low-power and performance-aware DFT techniques
- Experience working in high-volume manufacturing environments
If you are interested in this opportunity, please submit your updated resume in MS Word format along with your expected hourly rate to [Insert contact email or Phone #].
Rick P
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