Senior Design for Test (DFT) Engineer

Key Responsibilities: Develop and execute verification plans for DFx features including: Scan (stuck-at, transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Create and maintain testbenches using SystemVerilog/UVM for DFx validation. Verify: Scan chain integrity and connectivity Test mode functionality and coverage ATPG pattern validation and debug BIST controllers and memory test logic Technical Skills & Expertise: Strong knowledge of DFT/DF

Role: Lead ASIC DFT Engineer Location: San Jose, CA (Remote, PST time zone preferred) Work Setup: Remote, PST time zone preferred Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) DFT Architecture definition. Must Full chip / Sub system level DFT activities Must Scan & compression (EDT) implementation Must LBIST implementation and verification any BIST exp is Must Coverage improvements (Spyglass work) Must ATPG Good to Have Role Summar

Job Title: DFx Verification Engineer (DFT Verification) - Semicon companyLocation: Santa Clara, CA (Onsite)Duration: ContractOpen Positions: 15Experience: 4+ Years Role OverviewWe are looking for skilled DFx Verification Engineers with strong experience in Design-for-Test (DFT) verification. The ideal candidate will be responsible for validating DFx features including scan, BIST, JTAG, and low-power test scenarios using SystemVerilog/UVM-based environments. Key ResponsibilitiesDevelop and execut

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, throug