Verification Engineer


Microgreen Technologies LLC
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Job Details
Skills
- Cadence
- Debugging
- FOCUS
- Formal Verification
- Perl
- Python
- SVA
- Scripting
- Synopsys
- SystemVerilog
- UVM
- Venture Capital
- Videoconferencing
- Tcl
Summary
Title - Verification Engineer 4
Location: Austin, TX (Onsite)
PREFERRED EXPERIENCE:
- Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)
- Strong proficiency in System Verilog Assertions (SVA) and formal property specification
- Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
- Familiarity with scripting languages (TCL, Python, Perl) for flow automation
- Extensive experience in design verification with a strong focus on formal verification
- Expertise in System Verilog and UVM-based verification methodologies - Nice to have
Comments for Suppliers:
- Formal verification - use of Jasper or VC formal tools, Able to write/debug formal properties, have hands-on FPV or SEQ, hands-on atleast 3-5 yrs on the above requirements.
- Dice Id: 91109870
- Position Id: 9137197
- Posted 1 day ago
Company Info
A great team is the sum of its people. We are looking for those who want to make a difference with their talents and are looking to grow and learn EVERY.SINGLE.DAY.
Do you consider yourself an innovator? Do you measure each day by what you have accomplished? Read more.
From our business analysts who help identify the next opportunity to partner and addess a healthcare problem to our data visualization and AI/ML engineers who are adept with the latest technologies to our client support specialists who make sure that we are meeting and exceeding expectations, each team member is vital and we want to grow together. Collaboration, respect, and great work-life balance are key in our work culture.
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Account Manager @ Microgreen Technologies LLC
