Austin, Texas
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Yesterday
Title - Verification Engineer 4 Location: Austin, TX (Onsite) PREFERRED EXPERIENCE: Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)Strong proficiency in System Verilog Assertions (SVA) and formal property specificationExperience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysisFamiliarity with scripting languages (TCL, Python, Perl) for flow automationExtensive experience in design veri
Easy Apply
Contract, Third Party
Depends on Experience
