DDR Engineer

Job Title:DDR Engineer Location: Sanjose,CA Key skills: Zebu, FPGA , DDR (All generations) , ARM, DDR PHY, logic analyzers, oscilloscopes, and simulation waveforms Ensuring DDR PHY and controller designs adhere strictly to JEDEC standards (DDR4/DDR5/LPDDR5/LPDDR6) Using simulators (e.g., VCS) and emulators (e.g., ZeBu, Cadence Palladium) to debug design failures and root cause issues before tape-out. Validating power-sensitive LPDDR5 states, including self-refresh and deep power-down modes. Ru

Key skills: Zebu, FPGA , PCIe(All generations) , PCIE Serdes, ARM Highly skilled engineer to work on validating and debugging the the ULTRA low power designs on emulation and post-silicon platforms. Develop and execute test plans in C to validate the Features. In-depth knowledge of one or more peripheral protocols and specifications Bare metal/Linux driver development, Firmware development experience, and excellent C programming skills. Platform/Board-level debug experience and understanding (ad

Job Title: PCIE Engineer Location: San Jose,CA Key skills: Zebu, FPGA , PCIe(All generations) , PCIE Serdes, ARM Higly Skilled Engineer to work on validating and debug the the ULTRA low power designs on emulation and post silicon platforms. Develop and execute test plans in C to validate the Features. In depth knowledge of one or more peripheral protocols and specifications Bare metal/Linux driver development, Firmware development experience and excellent C programming skills. Platform/Board le

UFS Engineer Key skills: Zebu,FPGA,UFS,ARM Develop and execute verification test plans for UFS host IP within a System-on-Chip (SoC) environment using tools like emulation platforms (Veloce, ZEBU, HAPs). Debug failures using waveform viewers and log files to isolate and root cause issues in UFS protocols and bus interconnects Create pre-post silicon Validation C bases Test content. Enable firmware-driven validation on emulation platforms to integrate UFS driver-level software with hardware. Vali