Silicon Validation Software Engineer: CPU and Memory Hierarchy

Austin, TX, US • Posted 5 hours ago • Updated 5 hours ago
Full Time
On-site
Fitment

Dice Job Match Score™

🛠️ Calibrating flux capacitors...

Job Details

Skills

  • Writing
  • AIM
  • Logic Synthesis
  • Collaboration
  • Product Engineering
  • ROOT
  • Architectural Design
  • Computer Science
  • Electrical Engineering
  • Computer Engineering
  • CPU
  • Caching
  • System On A Chip
  • C
  • C++
  • Scripting
  • Python
  • Debugging

Summary

Would you like to work on SW that runs on every Apple phone, pad, and Mac computer in the world? Join our team of experienced SW engineers and debuggers in validating Apple's world class silicon. In this highly visible role you will be writing functional validation SW for the CPUs, caches, and memory subsystem of our SoCs, with the aim of identifying logic design and circuit bugs. You will be a SW developer for a system validation tool used widely across Apple's Silicon Engineering group, and will collaborate with SoC design and product engineering teams to debug and drive silicon issues to root-cause.

Validate CPU cores, cache coherency, and memory hierarchy behavior on post-silicon platforms.\nDevelop targeted stress tests to expose incorrect behavior under varying operating conditions(voltage, frequency, and temperature).\nPartner with design and architecture teams to correlate silicon behavior with intended micro architectural design.\nCatch incorrect silicon behavior and issues before product release.\nIdentify sensitivity to PVT shifts, including incorrect behaviors and intermittent failures.\nCollect and analyze silicon data (logs, counters, traces) to understand system behavior across operating conditions.\nProvide actionable feedback to PVT and other teams to refine operating limits

BS in Computer Science, Electrical Engineering, Computer Engineering, or related field with a minimum of 3 years relevant industry experience.\nExperience in post-silicon validation, PVT, system bring-up, or silicon debug.

Strong understanding of CPU microarchitecture, cache coherency, and memory hierarchy.\nKnowledge of SoC-level power, clocking, and voltage domains.\nExperience working with PVT, reliability, or silicon characterization teams.\nProficiency in C/C++ and scripting (Python) for automation and analysis.\nHands-on experience debugging real silicon across voltage, frequency, and temperature corners.\nAbility to communicate complex silicon issues clearly to cross-functional partners.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 90733111
  • Position Id: c0ef46c13d3ac327a69e1973e76af173
  • Posted 5 hours ago
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