Design Engineer / RTL Synthesis

Job Details: Job Description: Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our FPGA compiler and development tools are central to enabling customers to efficiently design, optimize, and deploy complex hardware systems on advanced FPGA platforms. Position Overview Altera is seeking a FPGA Development Tools Engineer to join our Synthesis team, focused on advancing the next generation of FPGA compilat

This position is for a Physical Design Engineer based in Sunnyvale, CA. The successful candidate will be responsible for driving RTL synthesis and optimization to achieve performance, power, and area goals for complex ASIC/SoC designs. They will work closely with various teams to ensure optimal timing, congestion, and power distribution in the design. ResponsibilitiesDrive RTL synthesis and optimization to achieve performance, power, and area (PPA) goalsPerform floorplanning for complex ASIC/SoC

Job Description Onsite 3 days in Sunnyvale, CA Job Description About the role: Design Verification engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement. Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run a

Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm-Atheros, a.k.a. QCA is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role involves ownership and leading Static timing closure and synthesis for complex low-power WiFi SoCs and sub-syste