IC Packaging Design Engineer

Chandler, AZ, US • Posted 2 days ago • Updated 2 days ago
Contract Corp To Corp
Contract W2
On-site
$50 - $60/hr
Fitment

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Job Details

Skills

  • signal integrity (SI)
  • power integrity (PI)
  • IC Packaging

Summary

Role: IC Packaging Design Engineer (Contract)

Location: Chandler, Arizona or Hillsboro, Oregon (Onsite)
Employment Type: Long-Term Contract

 

Job Description:

About the Role

We are seeking experienced IC Packaging Design Engineers to support advanced semiconductor packaging programs. The ideal candidates will possess strong expertise in package and substrate design, with hands-on experience in leading package design tools and a deep understanding of performance, manufacturability, and reliability considerations.

 

Required Technical Skills

  • Strong hands-on experience with Siemens (Mentor) Xpedition (XPD).
  • Alternative experience with Cadence Allegro, Advanced Package Designer (APD), or SiP tools is also acceptable.
  • Solid understanding of semiconductor packaging technologies, package architectures, and substrate design methodologies.

Key Responsibilities

  • Develop and implement physical design and layout solutions for advanced IC packages.
  • Perform substrate design and package layout activities while ensuring adherence to design specifications.
  • Execute signal integrity (SI) and power integrity (PI) aware package designs.
  • Optimize package designs for performance, manufacturability, yield, reliability, and cost efficiency.
  • Ensure compliance with package design rules, technology constraints, and industry standards.
  • Collaborate with cross-functional teams including silicon, system, SI/PI, manufacturing, and reliability engineering teams.
  • Support design reviews, issue resolution, and continuous process improvements throughout the product development lifecycle.

Preferred Experience

Candidates should demonstrate expertise in one or more of the following areas:

  • Physical package design and layout.
  • Substrate design and routing methodologies.
  • SI/PI-aware package implementation.
  • Design for manufacturability (DFM), design for reliability (DFR), and yield optimization.
  • Package design rule verification and compliance.
  • Advanced semiconductor packaging technologies, including multi-die, SiP, or high-performance package solutions.

 

We are an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, sexual orientation, or gender identity), national origin, citizenship status, age, disability, genetic information, protected veteran status, or any other characteristic protected by applicable law.

 

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 91081485
  • Position Id: 9015650
  • Posted 2 days ago
Contact the job poster
PR

Prasanth Rajendran

Recruiter @ Galent
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