IC Packaging Design Engineer

IC Packaging Design Engineer LOC: Chandler, AZ or Hillsboro, OR (ONSITE) Longterm Contract 1 Year + No openings : 4 Skills Required Bachelors or Masters degree in Electrical /Electronics Engineering Experience Tier: Senior-level (primary); Mid-level (secondary) Senior-Level: ~10+ years in IC packaging / package design Mid-Level: 46+ years (MS) or 6+ years (BS) in IC packaging / package design Strong hands-on experience in Siemens (Mentor) Xpedition (XPD); Alternatively: Cadence Allegro/Adva

Job Title: IC Packaging Design Engineer Location: Chandler, AZ or Hillsboro, OR (100% Onsite) Duration: Long-Term Contract (12+ Months) Employment Type: C2C / W2 Openings: 4 Job Description We are seeking experienced IC Packaging Design Engineers with strong expertise in package substrate design and advanced package layout. The ideal candidate should have hands-on experience with Siemens (Mentor) Xpedition (XPD) or Cadence Allegro Advanced Package Designer (APD/SiP) and a solid understandin

Top Mandatory Skills: 7+ years of advanced semiconductor packaging experience.Hands-on experience with 2.5D & 3D packaging technologies.Strong experience with chiplet architectures and heterogeneous integration.Experience with multi-die package design, silicon interposers, TSV, and advanced substrate technologies.Experience supporting AI/HPC semiconductor products from concept through production.Strong knowledge of package assembly, manufacturing, reliability, yield improvement, and qualificatio

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