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IC Packaging Design Engineer
LOC: Chandler, AZ or Hillsboro, OR (ONSITE)
Longterm Contract – 1 Year +
No openings : 4
Skills Required
Bachelor’s or Master’s degree in Electrical /Electronics Engineering
Experience Tier: Senior-level (primary); Mid-level (secondary)
• Senior-Level: ~10+ years in IC packaging / package design
• Mid-Level: 4–6+ years (MS) or 6+ years (BS) in IC packaging / package design
Strong hands-on experience in Siemens (Mentor) Xpedition (XPD); Alternatively: Cadence Allegro/Advanced Package Designer (APD / SiP)
Experience:
Strong hands-on experience in Siemens (Mentor) Xpedition (XPD); Alternatively: Cadence Allegro/Advanced Package Designer (APD / SiP)
Candidates should have experience in the below domains:
• Physical Design & Layout
• Substrate design and layout
• SI/PI aware design implementation
• Design for performance, manufacturability, yield, and reliability
• Design rule compliance
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•
Yesterday
IC Packaging Design Engineer Experience: Strong hands-on experience in Siemens (Mentor) Xpedition (XPD); Alternatively: Cadence Allegro/Advanced Package Designer (APD / SiP) Candidates should have experience in the below domains: Physical Design & LayoutSubstrate design and layoutSI/PI aware design implementationDesign for performance, manufacturability, yield, and reliabilityDesign rule compliance
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Contract
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Chandler, Arizona
•
Today
Job Title: IC Packaging Design Engineer Location: Chandler, AZ or Hillsboro, OR (100% Onsite) Duration: Long-Term Contract (12+ Months) Employment Type: C2C / W2 Openings: 4 Job Description We are seeking experienced IC Packaging Design Engineers with strong expertise in package substrate design and advanced package layout. The ideal candidate should have hands-on experience with Siemens (Mentor) Xpedition (XPD) or Cadence Allegro Advanced Package Designer (APD/SiP) and a solid understandin
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Full-time, Part-time, Third Party, Contract
Phoenix, Arizona
•
9d ago
Top Mandatory Skills: 7+ years of advanced semiconductor packaging experience.Hands-on experience with 2.5D & 3D packaging technologies.Strong experience with chiplet architectures and heterogeneous integration.Experience with multi-die package design, silicon interposers, TSV, and advanced substrate technologies.Experience supporting AI/HPC semiconductor products from concept through production.Strong knowledge of package assembly, manufacturing, reliability, yield improvement, and qualificatio
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Third Party, Contract
Depends on Experience
Phoenix, Arizona
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Today
Job Description Job Title: Principal PCB & Substrate Layout Engineer Pay Rate: $98/hr. Location: Phoenix, AZ Zip Code: 85034 Job Type: Contract Job Duration: 7 Months Schedule and Shift: 9-80 A|1st Shift|09:00 AM|N Keyword's: #Phoenixjobs; #PrincipalPCBjobs; #SubstrateLayoutEngineerjobs; #INDSUB Start Date: Immediate We provide a competitive pay and benefits package. This position is offering a pay rate of $98/hr. however, Belcan considers several factors when extending an offer, including but n
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Full-time
USD 98.00 per hour
