Role: Design Verification Lead
Location: Sunnyvale onsite
Job Type: Contract
Interview: Phone/Video
Job Description:
Experience: 12+ Years
Role: Lead - SoC/Sub-System Design Verification
About the Role
We are seeking an experienced Design Verification Lead to drive SoC-level verification strategy, lead high performing teams, and ensure first time right silicon. This role requires deep technical expertise, strong leadership, and the ability to influence cross functional teams while working in a fast paced environment.
Your Responsibilities
Lead an SoC Verification team, owning verification of the SoC and integration of its subsystems and flows.
Define, drive, and execute verification strategy, including test plans, requirements, environments, tools, and methodologies.
Review architecture specifications; collaborate with architects and RTL designers to assess impacts of architectural changes.
Create, Develop and maintain UVM/SystemVerilog-based testbenches for block, subsystem/cluster, and full chip verification.
Drive functional coverage, simulation strategies, emulation plans, and formal verification usage where applicable.
Perform and guide Gate-Level Simulation (GLS) bring-up, timing simulations, and signoff activities.
Debug complex SoC level issues across simulation, emulation, and silicon like environments.
Mentor and coach team members, fostering technical growth and excellence across the team.
Collaborate with cross functional stakeholders to deliver robust SoC verification solutions and ensure on schedule, high quality deliverables.
Your Profile / Required Qualifications
12+ years of experience in SoC design and verification.
Strong expertise in UVM, UPF, and protocol VIPs.
Proven ability to define and execute verification strategies at SoC and subsystem levels.
Hands on experience with AMBA protocols (AXI, AHB, APB) and at least one high speed or memory protocol.
Proficient in SystemVerilog, VHDL, Python, and TCL scripting.
Deep understanding of functional coverage, constrained random verification, simulation, emulation, and formal methods.
Experience participating in or driving architecture reviews and reacting to design/architecture changes.
Strong debugging skills with the ability to work independently in fast-paced environments.
Demonstrated ability to lead teams, influence stakeholders, and deliver strategic technical solutions.
Master s degree in electrical engineering, Computer Science, or a related field.
Nice to Have
Experience with performance verification.
Hands on exposure to formal verification methodologies.
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