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San Jose, California
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(Local Candidates Only) FPGA/RTL Design Engineer San Jose, CA - 100% Onsite 6 + Months $58-60/HR Interview Process: Onsite Top Must-Have Skills: RTL Design FPGA experience: Design, simulation, synthesis, and implementation Vivado experience TCL and Python scripting Job Duties & Responsibilities: Participate in all phases of the product development cycle, including architecture, design, prototyping, validation, productization, and support of IPs. RTL Development: Design, verify, and validate
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$58 - $60 per hour
