DFT Engineer

Job Title: DFT Engineer Location: Santa Clara, California. Client has relaxed the JD, and ATPG experience is not mandatory for candidates to submit going forward. More of the DFx skills and other DFT skills are required. Job details:- Familiarity with the Siemens suite of DFT tools DFT insertion for SCAN (with SSN) and MBIST MBIST Repair Implementation and Verification Generating collaterals for Test Timing and Place and Route Expertise in IJTAG 1687 standard and good at understanding ICL and P

Title: Design for Test (DFT) Engineer Location: Hybrid (Travel to Santa Clara) Duration: 1year Key Skills & Experience 3+ years of experience working as a DFT Engineer.Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite.Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing.Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improv

DFT (Design for Test) Engineer. Location: Santa Clara, CA Key Skills & Experience Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite. Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing. Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improvement. Experience with MBIST (Memory Built-In Self-Test), including memory test ar

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Required Skills & Qualifications 4+ years of hands-on experience in DFT and ATPGfor SoC or ASIC designsStrong understanding of DFT fundamentalsincluding controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Tes