IC Layout Designer

Location:REMOTEDuration: ~12 months (Immediate start through Q1 next year)Team Size: ~10 Engineers (Mix ofDesign & DV )Question from hiring manager on prior submital: Can you also check with the candidates on their recent hands-on experience with RTL design using SystemVerilog, & working on IPs with multiple clock domains?1. RTLDesignEngineerKey ResponsibilitiesOwn micro-architecture definition from high-level functional specificationsDevelop and implement RTL for complex digital blocksDrive dig

Job Description Title: Senior Staff GPU Physical Design Engineer Location: Austin, TX or San Jose, CA. onsite strongly preferred Need: GPU or high-performance SoC experience. Advanced node (?5nm). Full block ownership Position Summary We are seeking a Senior Staff GPU Physical Design Engineer for our client to work on the physical implementation of high-performance GPU and system-level IP, driving execution across synthesis, place-and-route, timing closure, and signoff for their advanced tech

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. As a Sr. Principal Application Engineer, you will be responsible for pre-sales technical campaigns to help sell EDA tools used to design printed circuit boards. The successful candidate will work closely with sales in supporting technical campaigns by creating and conducting product presentations and demonstrations, and some customer training and deployment work. This is a customer-faci

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Business Overview Deliver Emulation and Prototyping assisted verification products using virtualization (SW) technologies to accelerate and shift left SW-driven pre-silicon verification of advanced SoC designs. Job Description This Principal Product Engineer position is with the Virtual Protocols Product Engineering Team, responsible for the successful field readiness and customer dep